MASTER ADVANCED REFERENCE MANUALPlease do not copy this manual.This manual is reproduced here as it is now unavailable anywhere else. It issupplied on a non profit making basis to individuals who may require it. Ifanyone has any objection to this copy being supplied to the few BBC users thatmay require it, please let me know and I will remove it from circulation.If you are the owner of the copyright of this manual and would like to releaseit to the Public Domain, I would be very grateful if you would contact me.Chris Richardson8BS17 Lambert Park RoadHedonHullHU12 8HFUKTelephone 01482 896868Email chris@8BS.karoo.co.ukWebsite http://www.karoo.net/8bsThe AdvancedReference ManualFor The BBC Master 128 MicrocomputerPublished by Watford ElectronicsPublished in the United Kingdom byWatford ElectronicsJessa House250 Lower High StreetWatfordWD1 2ANEnglandTelephone 0923 37774Telex 8956095Fax 01 950 8989ISBN 0 948663 05 7Copyright 1988 Watford ElectronicsAll rights reserved, This book is copyright, No part of this book can becopied orstored by any means whatsoever whether mechanical, photographical or electronicexcept for private study use as defined in the Copyright Act. All enquiriesshould be addressed to the publishers.While every precaution has been taken in the preparation of this book, thepublisher assumes no responsibility for errors or ommisions. Neither is anyliability assumed for damages resulting from the information contained herein.Please note that within this text. the terms :-Tube and Econet are registered trade marks of Acorn Computers LimitedView and Viewsheet are registered trade marks of Acornsoft LimitedDOS Plus, Concurrent DOS and C/PM are the registered trademark of DigitalResearch Inc.All references in this book to the BBC Microcomputer refer to the computerproduced for the British Broadcasting Corporation by Acorn Computers Limited.This book was computer typeset by Ian Bishop Laggett,Ideal Software Consultants, 11 Hathaway Close Luton, Bedfordshire,AcknowledgementsThanks to David Beil, Roger Cullis, Dave Futcher Adrian Bishop Laggett and allthose people who made the publication of this manual possible.CONTENTS1. Master Series architecture 12Introduction 12core pin A17 on either of the cartridge connectors. Note that in this case aclock source MUST be provided or the dynamic memories could be destroyed.Link between C and D - The cartridges are clocked by the 8MHz signal from thecomputer. This is a synchronous signal with the 2MHz (d2) signal, alsosupplied to the cartridges. Note that the link between A and B must also befitted.LK7 PCB track, made East: Video polarity - two-position link.The polarity of the video RGB signals is determined by this link. It issupplied as a track on the bottom of the PCB causing true polarity. This trackmust be broken and a piece of wire used to make the link West for negativepolarity.LK8 : Not present.LK9 : Not present.LK10 fitted for NTSC only: Channel Select - two position link.When used with NTSC VHF televisions, the modulator enables one of two channelsto be selected. Note that the computer as supplied for use in the UK is fittedwith a UHF modulator so LK1 0 is not fitted.L.K11 : Not present.LK12 Plug, made B (East): CSYNC/Cartridge Machine Detect - two-position link.Position A - This connection to the computer CSYNC line is provided forGENLOCK purposes.Position B - Certain hardware cartridges may need to detect whether they areplugged into a Master Series computer or an Acorn Electron. Master computersare shipped with this link in the B position causing a logic LOW to appear onpin Al 0 of the cartridges. The Electron has no connection to this pin.LK13 PCB track, made West: A to D converter reference select - two-positionlink.As shipped, this link is a track on, the bottom of the PCB causing the A-to-Dconverter reference voltage input to be 1.8V.If the LK13 track is cut then the voltage reference must be applied betweenanalogue ground and Vref on the external connector.If the LK13 track is cut and LK13 made East with a wire link, a precisionreference can be fitted in the position PR1 shown on the circuit diagram.LK14 PCB track, made: Serial data clock reference - one-position link.As shipped, this link is a track on the PCB connecting the CHROMA chip 1.23MHzoutput to the Serial Processor. This link is provided for production purposesand should not be modified.PAGE: 207LK15 PCB track, made West: PAL/NTSC select. two.position link.As shipped in the UK, this link is a track on the bottom of the PCB causing theCHROMA chip to encode colour information on to the television output in PALformat. If the track is cut and a wire link used to make the other side of thelink, then colour information will be encoded in NTSC. In general, televisionswithin the UK can only accept the PAL format.LK16 wire link, not fitted :Chrominance information luma trap bypass. one.position link.This link is not normally fitted. It is provided for those applications wherefiltering of the luminance information from the chrominance part of thetelevision signal is not required.LK17 : Not present.LK18 plug, made West: Paged ROM/RAM Select. two-position link.When fitted in the West position, this link causes 16Kbyte of RAM to appear ineach of the 'sideways' memory 'slots' 6 and 7.When fitted in the East position, a 32Kbyte ROM occupying slots 6 and 7 may beplugged into socket labelled IC41.LK19 plug, made West: Paged ROM/RAM Select. two-position link.When fitted in the West position, this link causes 16Kbyte of RAM to appear inone of the 'sideways' memory 'slots' 4 and 5.When fitted in the East position, a 32Kbyte ROM occupying slots 4 and 5 may bplugged into socket labelled lC37.LK20 : Not present.LK21 plug, not made: Light Pen Strobe to cartridge.This link is not normally made, so position B1 0 on the cartridges is merely aconnection from one to the other. When the shunt is fitted. the CRTC Light PenStrobe input is connected to B10. This is to facilitate GENLOCK and analternative LPSTB connection to the rear analogue connector.Master CompactTP1 - MAX232 -ve output.If the serial interlace is fitted, the voltage on this pin should be between-1 0v and-5v. A figure of -9v is quite typical.TP2 Machine 12Internal I/O 13External I/O 13 Internal Input/Output 14Slow peripherals 14Sound Generator 14Real time clock with RAM 14Configuration Status 15Clock 151MHz Internal I/O 15System VIA 152MHz Internal I/O 16 External Input/Output 171MHz External I/O 17Analogue Port 17Light Pen 172MHz External I/O 17External Second Processor 172. Circuit description 19Detailed Circuit Operation 243. Memory organisation 27Memory Map 27Random-Access Memory 28ROMSEL 30Overlaid RAM in ROM area 30DRAM timing 314. Slow data bus 32Memory Locations 32Slow Data Control Port 32Keyboard 33Sound Generator 33Real time clock/CMOS RAM 33CMOS RAM Allocation 33Real Time Alarm Functions 34RTCRAM Access Restrictions 355. Keyboard controller 37Keyboard Operation 37KBDENC connections 38Keyboard Matrix 40Timing diagrams 40Free running mode 40Column scan mode 41Row scan mode 416. Screen display 42Screen Output 42High Resolution Modes 42Teletext 43Hardware Scroll 43Video Output 44Video Processor 44Control Registers 45Miscellaneous Functions Control Register 45Palette Control Register 46Cathode Ray Tube Controller 46CRTC Multiplexer 48Internal Timing 49Hardware Scroll 49Refresh Control 49Multiplexing 49VDU driver 497. User Port 52Timers 52User Port Data Register 53User Port Data Direction Register 53Timer 1 Low Order Counter/Latch (R/W) 53Timer 1 High Order Counter (R/W) 53Timer 1 - Low Order Latch (R/W) 54Timer 1 High Order Latch (R/W) 54T2 Low Order Counter/Latch (R/W) 54T2 High Order Counter (R/W) 54Shift Register 54Auxiliary Control Register (R/W) 56Peripheral Control Register 57Independent Mode 57Interrupt Flag Register 58Interrupt Enable Register 59Example of motor control 598. Serial Processor 61UART 61SERPROC 61Buffer Components 61Control Register Settings 629. Peripheral bus controller 63Internal Timing 63Buffer Control 63Timer 63I/O Definition 64AC Parametric Test Information Timing Specifications 65SA data latching point 66SL data latching point 66C Bus Drive Waveforms 67B Bus Drive Waveforms 68E bus drive waveforms 6910. 1MHz Bus 70Signal definitions 70Hardware requirements for 1MHz expansion bus peripherals 72Derivation of valid Page signals 73Address space allocation 73Page FC 73Page FD 74Timing requirements 7511. Machine Operating System 77Address space map 77Page 0 77Pages &1 to &D 78Pages &E to &7F 80Pages &80 to &BF 80Pages &C0 to &DF and page &FF 82Page &FC 82Page &FD 82The Second 32k of RAM. 82VDU Workspace 83VDU workspace allocations 84Extending the MOS 84Time-independent Functions 84Vectors in co-processors 85Vectors In Sideways ROM/RAM 85MOS Function Vector Table 86Entry pointed vectors 87Vectors without MOS entry points 87EVENTV 8BRK instruction 88BRK instruction in single processor systems 89BRK instruction in co-processor systems 90USERV 90KEYV 90VDUV 91UPTV 92FSCV 93INSV 94REMV 94CNPV 94NETV 95INDirect Vectors 95Time dependent functions 96EVENTV 9612. Dual processor systems 98Second processor architecture 98The Tube 99Tube Architecture 100Tube Protocols 101Operating System Usage 102Filing System Usage 103PARASITE Protocols 105Vectors 105Hardware Dependency 106Host Hardware - MAX232 +ve output.If the serial interlace is fitted, the voltage on this pin should be between5v and 1 0v.A figure of 9v is quite typical.PAGE: 208Test points TP1 and TP2 are positioned close to IC5 (North of the PCB).TP3 - connected to the CPU NMI pin.This should be generally at 5v while running, making excursions to 0v only whendisc and Econet are being used.TP4 - connected to the CPU IRQ pin.Check that this is not stuck either high or low when free running.TP5 - connected to the CPU SYNC pin.This is asserted during an op-code fetch by the processor, and is used byACCCONto ensure that the correct memory area is accessed at this time. If this iscontinuously high or low, then the processor has completely stalled.TP6 - This is connected to the processor READ/WRITE Line.This should change between 0v and 5v frequently (but not necessarilyregularly!)Test points TP3 to TP6 are situated South of the CPU IC28 (65C12) to thesoutheast of the PCB.PL7 - Not fittedallows the light pen strobe (LPTSTB) to be connected to the CRTC IC.PL9- pcb track made northIf set North, the video output will be normal, if set South the video outputwill be inverted. If change is required, cut circuit board track, and eitheruse tinned copper wire, or fit three pins, and select the required positionusing a mini shunt.PL10 - pcb track made eastIf set East, the RGB CSYNC signal will be inverted. If set West, it will benon- inverted. This is necessary for certain monitors. If change is required,cut circuit board track, and either use tinned copper wire, or fit three pins,and select the required position using a mini shunt.PL11 - plug made northIf set North, 32k ROM space banks 0 and 1 are assigned to the edge connector.If set South, 32k ROM space banks 0 and 1 are assigned to IC38.PL12 - plug made northIf set North, allows system ROM containing 64k bytes of code. If set South,allows ROM containing 128k bytes. Factory position is currently NORTH, but maychange to SOUTH in future production.PAGE: 209Circuit board modifications necessary for fitting optionalcomponents.VR1If a volume control is required for the loudspeaker, a preset potentiometerVR1 may be fitted. If this modification is done, first cut the circuit boardtrack joining two pins of VR1.FS1A fuse (FS1) may be fitted if required, first cut the track under FS1 on thePCB.L1/L2If further filtering (L1 and L2) is used, the tracks under L1 and L2 on themain PCB must be cut.PAGE: 210APPENDIX SEVENTHE MASTER 128CARTRIDGE INTERFACEThe Master Series Cartridge Interface is an enhancement of that of the ElectronPlus 1. The connections and any differences are noted below.Abbreviations used in this Appendix are as follows:AIL Active low.O/C Open Collector output.CMOS Complementary Metal Oxide Semiconductor.CPU Central Processor Unit i.e. the microprocessor.TTL Transistor-Transistor Logic.& A hexadecimal number follows.n As a signal prefix means Active low output(A/L).PCB Printed Circuit Board.Cartridge OrientationThe cartridge pinning in the Master Series machine is arranged as follows:Viewed from above Side ARom Nos 0 and 1 Side B Side ARom Nos 2 and 3 Side BFRONTComponents are normally mounted on to Side A of the PCB within the cartridge.PAGE: 211PinoutPins are described viewed from 'within' the cartridge i.e. an 'Input' is aninput to the cartridge. An 'output' is an output to the computer.Side A1 +5V - logic power supply 150mA max in a Master with co-processor fitted and with disc drives. 50mA max in an Electron Plus 1.2 nOE - Output Enable Input from AIL CMOS level. low during d2 period of system clock. It is intended to switch on the output buffers of cartridge memory devices. It is not guaranteed low at other times.3 nRST-System Reset Input from AIL CMOS level. low during a system reset. It is not synchronised to any clock.4 CSRW - chip select - Read/Write Input from CMOS level. Master Changes function according to the memory region that the CPU is addressing.106Parasite Hardware 106Non-interrupt protocols 106OSWRCH 106OSRDCH 106OSCLI 106OSBYTE 107OSWORD 107OSBPUT 108OSBGET 109OSFIND 109OSARGS 109OSFILE 109OSGBPB 110Interrupt driven operations 110Start-up protocol 113Register Addresses 113Tube protocols 113Host Protocols 113Check for presence of the Tube 114Claiming the Tube 114Initiating data transfer 115Transferring data 116Releasing the Tube 116Register Locations 116Tube/filing system interface 117LOAD/SAVE addresses 117Use of the Non Maskable Interrupt 118Claiming NMI workspace 118Hardware access to the NMI 11913. Z80 Second processor 120Operating system calls 120Faults and events 1216502 Faults 121Z80 Faults 121Events 121Escape processing 122Interrupt handling 122NMI Nonmaskable interrupt 122INT Interrupt request 122Z80 Monitor 122Z80 OSWORD call 123I/O Processor Memory Usage 124Screen Control 125BBC Microcomputer Control Codes 125Terminal Emulator Control Codes 125GSX Functions 126Character I/O under CP/M 126Device assignments 126The IOBYTE facility 127Device characteristics 129The System Patch Area. 13014. 80186 coprocessor 131Operating System Calls 131OSFlND 132OSGBPB 132OSBPUT 132OSBGET 132OSARGS 133OSFILE 133OSRDCH 133OSASCI 133OSNEWL 133OSWRCH 134OSWORD 134OSBYTE 134OSCLI 134Error Handling by the 80186 Monitor 135Error Handling by stand-alone languages or applications 13580186 Error Messages 136Escape Processing 13880186 Monitor 13880186 OSWORD call 14215. Disc filing systems 145DFS 145ADFS 146CP/M Disc Format 14716. ANFS 148Local buffering 148Operating System Commands 149*HELP 149*CDIR 149*FLIP 149*FS 150*I AM 150*LCAT 150*LEX 150*PASS 150*WIPE 151Extra Utils star commands incorporated in the ROM 151*POLLPS 151*PROT 151*UNPROT 152*PS 152*WDUMP 152*CONFIGURE commands. 152*STATUS commands 153Extra *OPT commands 153Printing 154Extra interfaces 154Enhancements to the filing system interface 154Write only files 154OSFILE 155OSARGS 155Error messages 155User Root Directory Reference Point 156Compatibility with DFS based software 157Additional library functionality 157Time and Date 1571/0 processor address space 157Automatic Bootstrapping 157Re-tries 158File server / Bridge net number translation 158Detection of wrong versions and ANFS 158Entry of hexadecimal numbers 159Events on reception 15917. Terminal emulator 160OSBYTE 96,x 160Terminal File Transfer 16018. Editor 161Buffer Transfer 161From the language to Editor 161From EDITOR to the language 16119. VIEW and VIEWSheet format 162Reserved Characters and File Format 162VIEW formatting characters 162Memory Format 163Number Registers 164VIEWSHEET data representation 164APPENDICES Appendix 1 Differences between Model B+ and Model B 165Appendix 2 Differences between Master 128 and Model B/B+ 171Appendix 3 Differences between Compact and Master 128 190Appendix 4 - Differences between ANFS and NFS 200Appendix 5 Changes introduced in Basic 4 203Appendix 6 - PCB selection links and test points 205Appendix 7 Cartridge interface 210Appendix 8 65C12 Instruction set 215INDEX 283PAGE: 11INTRODUCTIONThis book is intended for peripheral hardware designers and software writersand expands the information given in Reference Manuals Parts 1 and During accesses to &FC00 thru &FEFF it is equivalent to the CPU Read/Write line during nd2. For all other accesses, it is an Active High chip select for memory devices. It is not guaranteed low at other times. Electron CPU Read/Write line.5 A8 -Address line 8 Input from TTL level.6 A13 - Address line 13 Input from TTL level.7 A12 - Address line 12 Input from TTL level.8 d2 - CPU clock Input from CMOS levels. computer's d2 output.9 -5V - Negative supply voltage. 20mA max. This -5V may not be available on all Acorn Cartridge Interfaces. To ensure compatibility, negative voltages should be generated within the Cartridge if required.10 CSYNC/MADET Master There are two functions dependent upon link 12 in the computer. E/nB - the default function. It enables Cartridges to know which machine they are plugged into. It is connected to 0V in the Master, (and unconnected in the Electron). Link 12 is set to position B. CSYNC - Composite Sync. Input from TTL levels. System Vertical & Horizontal sync is made available for Genlock use. Set Link 12 to position B. Electron Unconnected PAGE: 21211 RnW/READY Master R/W - Data Direction control Input from TTL levels. System data buffer direction control. If low, cartridges are being written to; if high and selected, they may drive the bus during d2. Electron READY - CPU wait state control O/C AIL output. When driven low, this line will cause the CPU to extend its cycle until READY is released. Only works with CMOS CPUs and only on READ cycles.12 nNMI - Non-maskable Interrupt O/C A/L output. Connected to system NMI line.13 nlRQ - Interrupt Request O/C AIL output. Connected to the system 1 RQ line.14 nlNFC - lnternal Page &FC Input from TTL levels. AIL. Memory Active decode input. Master When bit IFJ in the Master ACCON register (via &FE34) is set, all accesses to &FC00 thru &FCFF will cause this select to become active. Electron Not applicable.15 nlNFD - Internal Page &FD Input from TTL levels. AIL. Memory Active decoded input. Master When bit IFJ in the Master ACCCON register (via &FE34) is set, all accesses to &FD00 thru &FDFF will cause this select to become active. Electron Not applicable.16 ROMQA - Memory paging select Input from TTL levels. This is the least significant bit of the ROM select latch located at &FE30 in the Master, and &FE05 in the Electron.17 Clock Input/Output TIL levels. Master Links on the computer select one of two functions: a) 16Mhz output to computer (Link DB only). b) 8Mhz Input to cartridge (Link CD in addition to AB). The user should ensure that the links are set correctly, and that there is proper termination. Normally only AB is linked in the computer. Electron 16MHz Input.18 nROMSTB/nCRTCRST TTL levels. Master nCRTCRST is an Active Low Output signal of the system CRTC reset input. It is provided for Genlock use.PAGE: 213 Electron nROMSTB is an Active Low Input which selects &FC73. It is intended to be used as a Paging Register.19 ADOUT - System audio Output. Filtered output of the sum of all audio inputs to the computer. No significant load should be taken from this pin.20 AGND - Audio Ground. The zero volt return for ADOUT. It should be used instead of system 0V to minimise audio noise.21 ADIN - System audio input. Master An input to the computer's audio circuitry. It presents an impedance of at least 1 K ohm. Only one cartridge using this input should be connected to the computer at one time. Electron This is a connection from one cartridge to the other.22 0V - Zero volts. System earth return for digital signals. SIDE B 1 +5V - Logic power supply 150mA max in a Master with Co-processor fitted and with disc drives. 1 0mA max in an Electron Plus 1.2 A10 - Address line 10 Input from TTL levels.3 D3 - Data bus line 3 Input/Output TTL levels.4 A11 - Address line 11 Input from TTL levels.5 A9 - Address line 9 Input from TTL levels.6 D7 - Data bus line 7 Input/Output TTL levels.7 D6 - Data bus line 6 Input/output TTL level 2It contains software and hardware reference material, with applicationguidelines which anyone who is attempting a major project for the first timewill find particularly useful. The remaining chapters contain information onthe Acorn-designed semi custom chips and a number of detailed appendiceshighlight the differences between the Master 128 and other Acorn modelsincluding the Compact and the Electron.It has been assumed that the reader has a good understanding of basicelectronics and computer terminology.PAGE: 12 1 THE MASTER SERIESARCHITECTUREIntroductionThe Master Series is based on and extends the architecture of the Acorn BBCModel B microcomputer The heart of the computer is a comprehensive machineoperating system (MOS) which controls and organises the communicationsbetween a central processing unit (CPU) and applications software, peripheraldevices. such as video displays and printers and filing systems which act assources and stores for data. Language interpreters and compilers may beprovided to convert high level languages into a format usable by the MOS.Alternatively, the applications may be in object code which runs directly onthe CPUThe simplest version of the computer (the Master 128) has a single processorwhich performs all of these executive functions In other computers of theseries, responsibility is split between a base processor which handlesinput/output(I/O) operations and a language processor which performs thecalculations and other data operations associated with the applications'tasks. In general, the language processor will be selected for its suitabilityfor a particular application and will be different from the base processor.Core MachineAll input/output (I/O) computing is performed by a 65C12 CPU with its principalancillary components.128 Kbyte of dynamic random access memory (DRAM)Special expansion options allow a further expansion of 64 Kbyte.Dedicated hardware can be used to expand this almost indefinitely.262 Kbyte of read-only memory (ROM)Special expansion options allow a further expansion of approximatelyhalf a megabyte of ROM. Plug in cartridges are available which acceptup to 256 Kbyte of ROMPAGE: 13Internal I/OInternal versatile interface adapter (VIA)This services a 93-contact keyboard with two key rollover, a three channelsound generator with additional noise channel and a battery-backed real-timeclock with fifty bytes of RAM.External versatile interface adapter (VIA)This services the parallel printer port and the user portCo-processorsThese consist of an additional CPU with associated memory. They dependentirely on the main processor for all I/O operations.ExternaI I/OVideo displayA 6845 CRT controller formats the output for RGB, composite video andPAL/NTSC connectors.Analogue to Digital ConverterA four channel A-D converter provides ten bit binary conversions in 5ms. Theabsolute accuracy will depend on the conditions of useTape interfaceFacilities to both save and retrieve data from audio cassettesDisc InterfaceFacilities to both save and retrieve data from standard Shugart connectedmedia. Filing systems data encoded in FM or MFM format.Network InterfaceConnection to ECONET is provided by a 68B54 advanced data link controllerThis is fitted on a daughter board and may be an optional extra (standard onthe ET machine)1MHz BusStandard BBC computer 1 MHz bus.External Second ProcessorAn external second processor may be connected Selection of either internalco-processor or external second processor is performed by software Onlyone second or co processor can be active at a timeCentronics PrinterPort Connection for a standard parallel printerUser PortThe user port is an eight-bit bi-directional bus with two extrahandshaking/serial lines. These are unbuffered.RS423A serial RS423 port This is an enhanced version of the RS232CspecificationPAGE: 14Audio OutputThe output from the sound generator is amplified to a speaker and provided ata phono-style connector. Sound transfer to and from ths.8 D5 - Data bus line 5 Input/output TTL levels.9 D4 - Data bus line 4 Input/Output TTL levels.10 nOE2/LPSTB - O/P Enable/Light Pen Strobe Input from TTL levels. Master With link 21 removed in the computer, this pin provides a connection between the two cartridges. With the link in place, the pin forms a connection to a pull-up resistor in the computer to +5V. The connection is also made to the CRTC Light-Pen Strobe and interrupt structure. Electron This provides an additional AIL enable for ROMs in the Electron. This corresponds to ROM position 13 and responds quickly to Service Calls. It is low during the AIL portion of d2. It is not guaranteed high at other times.PAGE: 21411 BA7 - Buffered address line 7 Input from TTL levels. Master This line holds addresses valid for 125nS after d2 goes low. Electron This is not buffered nor held valid for an extended period in the Electron.12 BA6 - Buffered address line 6 Input from TTL levels. See pin 11.13 BA5 - Buffered address line 5 Input from TTL levels. Seepin 11.14 BA4 - Buffered address line 4 Input from TTL levels. See pin 11.15 BA3 - Buffered address line 3 Input from TTL levels. See pin 11.16 BA2 - Buffered address line 2 Input from TTL levels. See pin 11.17 BA1 - Buffered address line 1 Input from TTL levels. See pin 11.18 BA0 - Buffered address line 0 Input from TTL levels. Seepin 11.19 D0 - Data bus line 0 Input/Output TTL levels.20 D2 - Data bus line 2 Input/Output TTL levels.21 D1 - Data bus line 1 Input/Output TTL levels.22 0V - Zero volts Digital signal Earth return.PAGE: 215APPENDIX EIGHT65C12 INSTRUCTION SETThis appendix lists each 65C12 instruction on a separate page along withdetails ofthe status flags affected and a brief description.A number of new mnemonics which do not exist on the 6502 are provided on the65C12 which also has one new addressing mode called '(indirect zero page)'.Thisis similar to '(indirect,X)' and '(indirect),Y' but does not require the X orY registersto be set to zero.The new 65C12 mnemonics are:BRA Branch alwaysCLR Clear memory (also STZ)DEA Decrement accumulatorINA Increment accumulatorPHX Push X register onto stackPHY Push Y register onto stackPLX Pull X register from stackPLY Pull Y register from stackSTZ Clear memory (also CLR)TRB Test and reset bitsTSB Test and set bitsThe Rockwell R65C02, which is normally fitted within the 6502 and Turbo Secondprocessors, has two instructions which do not exist on the 65C12 and whichhave to be assembled by hand.BBR Branch on bit resetBBS Branch on bit setIn the tables listing the various op.codes the time taken to execute eachinstruction is given as a number of cycles. Each cycle represents:0.5ms on a BBC model B0.33ms on a Master or 6502 Second Processor0.25ms on a Master Turbo Co-processor.PAGE: 216ADCFlags: N V Z CADD to Accumulator with CarryOperationA,C = A + M + CDescriptionAdds the contents of a memory location to the Accumulator. If the carryflag is set then 1 is also added. If the result overflows then the carry flagwill be set, allowing multiple byte addition.Op. Code Addressing Mode Assembly Lang Bytes Cycles&69 Immediate ADC #dd 2 2&65 Zero Page ADC aa 2 3&75 Zero Page,X ADC aa,X 2 4&72 (Indirect Zero Page) ADC (aa) 2 5**&6D Absolute ADC aaaa 3 4&7D Absolute,X ADC aaaa,X 3 4*&79 Absolute,Y ADC aaaa,Y 3 4*&61 (Indirect,X) ADC (aa,X) 2 6&71 (Indirect),Y) ADC (aa),Y 2 5** Add 1 Cycle if page is crossed** Add 1 cycle if in decimal codePAGE: 217ANDFlags: N ZAND Memory with AccumulatorOperationA=A AND MDescriptionA logical AND is performed between the accumulator and a memorylocation. The result is left in the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&29 Immediate AND #dd 2 2&25 Zero Page AND aa 2 3&35 Zero Page,X AND aa,X 2 4&32 (Indirect Zero Page) AND (aa) 2 5&2D Absolute AND aaaa 3 4&3D Absolute,X AND aaaa,X 3 4*&39 Absolute,Y AND aaaa,Y 3 4*&21 (Indirect,X) AND (ae modemModem Connection for a modem with both dial pulse and dual tone multi frequencydialling.Internal Input/OutputSlow peripheralsThese are subsystems which are provided with data from port A of the system VIAThis data is stable until next programmed by the CPUSound GeneratorThe sound generator is an SN7694A device, which generates three sound channelsplus one pseudo random noise channel The full description of it is found in themanufacturers data sheet. It receives a reference clock of 4MHz from centraltiming. The output can be connected by screened cable to the optional modemThis output is mixed on the modem board to generate dialling tones for DTMFexchanges where the modem hardware does not provide such tones itselfReal time clock with RAMA 146818 RTC and RAM chip is provided with battery backed supply The chipoperation is described in the manufacturers data sheet. There are three AA sizebatteries which normally keep the RAM backed-up for at least a year (dependingon how much the machine is NOT used)The keyboard mounted battery is charged whilst the computer is running from themains supply An over charge prevention circuit is provided with the followingaction:-a) Upon switch on, charging current of about 30mA is appliedb) After approximately 15 minutes the charging current falls to 1 mA.c) Trickle. charging continues at 1 mA for as long as mains power isapplied.The minimum charge burst is designed to provide battery back-up over a weekendafter just a few minutes operation. A 10mf capacitor is connected across theclock chip supply connections to prevent loss of data in the event ofaccidental battery disconnectionPAGE: 15Configuration StatusFifty bytes of CMOS RAM are available within the chip Twenty of these are usedby the operating and filing systems for initial configuration of the hardware.Of the remainder ten are reserved for future use by ACORN, ten are for 'thirdparty' use and the remainder are for the userClockThe clock operates from a 32 768KHz crystal oscillator A trimming capacitor isprovided as is a test point with the buffered clock output. Year month. dayhour minute and second information is provided with automatic leap year (butnot automatic leap century) correction. An alarm is also included within thechip, but there is no operating system support for this facility. An optionalnlRQ connection can be made to the CPU from the clock chip, enabling the alarmto change program flow.Operation of the clock chip in this manner involves direct manipulation of thechip control signals and should only be attempted by competent programmers.Acorn Computers are not responsible for incorrect programming by theuser/software supplier.If power is removed during an access to this chip, the chip select will becomeinvalid, with the possibility of write accesses being corrupted. This isavoided by inverting the chip select with a transistor whose collectorresistor is connected to the battery backed supply. As power fails to the maincircuitry the transistor base current reduces and the transistor switches offdeselecting the chip.1MHz Internal I/OVarious devices operate at a 1MHz bus rate. Only one internal I/O componentworks at this speed - the system VIA.System VIAA 6522 allows several sources to create maskable interrupts. The sources are:-a) CRTC vertical synchronisationb) A D converter; end of conversion signal.c) CRTC light pen strobe.d) Keyboard key detectIt also provides the slow data busPort B on this device generates and reads a number of internal hardware strobesPAGE: 16These are:-Port B Data Strobe Active LevelPort B Data Strobe Active LevelD7 DODXXXXXXX Clock Address HXDXXXXXX Clock chip enable HXXDXXXXX 'Fire' button 1 InputXXXDXXXX 'Fire' button 2 InputXXXXD000 Sound chip select LXXXXD001 Clock R/W LXXXXD010 Clock Data QXXXXD011 Keyboard enable QXXXXD100 CO Screen control LXXXXD101 C1 signals HXXXXD110 Caps Lock indicator LXXXXD111 Shift Loa,X) 2 6&31 (Indirect),Y) AND (aa),Y 2 5** Add 1 Cycle if page is crossedPAGE: 218ASLFlags: N Z CAccumulator Shift LeftOperationC = M7, M=M*2DescriptionShifts the contents of a memory location or the accumulator one bit to theleft. This operation effectively multiplies by two and leaves any overflowin the carry flag.Op. Code Addressing Mode Assembly Lang Bytes Cycles&0A Accumulator ASL A 1 2&06 Zero Page ASL aa 2 3&16 Zero Page,X ASL aa,X 2 6&0E Absolute ASL aaaa 3 6&1E Absolute,X ASL aaaa,X 3 7PAGE: 219BBRBranch on Bit ResetOperationBranch if bit=0DescriptionBBR is not normally available but does exist on the Rockwell R65C02which is usually fitted within the Master Turbo and 6502 SecondProcessors. If a bit in a zero page location is clear a branch will occur.Op. Code Addressing Mode Assembly Lang Bytes Cycles&0F Zero page, bit 0 BBR aa 3 5*&1F Zero page, bit 1 BBR aa 3 5*&2F Zero page, bit 2 BBR aa 3 5*&3F Zero page, bit 3 BBR aa 3 5*&4F Zero page, bit 4 BBR aa 3 5*&5F Zero page, bit 5 BBR aa 3 5*&6F Zero page, bit 6 BBR aa 3 5*&7F Zero page, bit 7 BBR aa 3 5*&0F Zero page, bit 0 BBR aa 3 5*&1F Zero page, bit 1 BBR aa 3 5*&2F Zero page, bit 2 BBR aa 3 5*&3F Zero page, bit 3 BBR aa 3 5*&4F Zero page, bit 4 BBR aa 3 5*&5F Zero page, bit 5 BBR aa 3 5*&6F Zero page, bit 6 BBR aa 3 5*&7F Zero page, bit 7 BBR aa 3 5** Add 1 Cycle if branch occurs oradd 2 cycle if branch crossed a page boundaryThis instruction is not available in the BASIC assembler and will have to beinserted using EQUBExample: Branch if bit 5 of zero page location &70 is 0 (reset)EQUB &5F \BBR op.code for bit 5EQUB &70 \zero page &70EQUB &09 \branch forward 9 bytesPAGE: 220 BBSBranch on Bit SetOperationBranch if bit=1DescriptionBBS is not normally available but does exist on the Rockwell R65C02which is usually fitted within the Master Turbo and 6502 SecondProcessors. If a bit in a zero page location is clear a branch will occur.Op. Code Addressing Mode Assembly Lang Bytes Cycles&8F Zero page, bit 0 BBS aa 3 5*&9F Zero page, bit 1 BBS aa 3 5*&AF Zero page, bit 2 BBS aa 3 5*&BF Zero page, bit 3 BBS aa 3 5*&CF Zero page, bit 4 BBS aa 3 5*&DF Zero page, bit 5 BBS aa 3 5*&EF Zero page, bit 6 BBS aa 3 5*&FF Zero page, bit 7 BBS aa 3 5** Add 1 Cycle if branch occurs oradd 2 cycle if branch crossed a page boundaryThis instruction is not available in the BASIC assembler and will have to beinserted using EQUBExample: Branch if bit 5 of zero page location &70 is 1 (set)EQUB &DF \BBS op.code for bit 5EQUB &70 \zero page &70EQUB &09 \branch forward 9 bytesPAGE: 221BCCBranch on Carry ClearOperationBranch on Carry ClearDescriptionIf the carry flag is clear this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&29 Relative BCC aa 2 *2* Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 222BCSBranch on Carry SetOperationBranch on Carry SetDescriptionIf the carry flag is set this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&B0 Relative BCS aa 2 2** Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 223BEQBranch on Result Equal to ZeroOperationBranch on Zero Flag=1DescriptionIf the zero flag is set this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytck indicator LNote: Q is the value of D after the port write operation is completed2MHz Internal I/OOnly one internal I/O component operates at this clock rate, the internalsecond processor TUBE. Its data bus is connected directly to the CPU databus. The second processor interface will only be specified as a hardware datatransfer definition. In this way, the actual second processor used will not beconstrained by this specification.The interface is a parallel port providing the following data access signals:-i) DO to D7 A bi-directional bus to TTL levels.ii) AO to A2 A uni-directional bus to CMOS levels.The following control and timing signals are provided:- HostCPU phi2 CMOS levels System Reset TTL levels HostCPU nlRQ This must be an 'open collector' node with an active low TTL level 8MHz timing reference TTL levels TUBE chip select CMOS levels Read/Write TTL levelsPAGE: 17External Input/Output1MHz External I/OAnalogue PortThis 15-way D-type connector provides access to an NEC mPD7002 four-channel,ten-bit analogue-to-digital converter. The sampled input is compared to a 1.8Vreference derived from three small signal diodes in series.A tracked link may be cut to deselect this reference. The user may then solderin a two-pin precision reference in the holes provided or supply an externalreference. Any user supplied reference should have a maximum voltage of 2.5V.An input voltage on any one of the four channels will be digitised when the AIDcontrol register is so instructed. Conversions are in the range 0 to 1.8V.The voltage reference is made available at the connector. Provision is madeon the board for an additional high stability reference, if required. A linkwill have to be made for the additional reference to be used. Conversionstake place in 5ms and the 'end of conversion' pulse causes an IRQ to begenerated by the system VIA.Two fire buttons are provided for with the connections I0 and I1. These areconnected to the system VIA and cause interrupts (as IRQ ) to be generated.Light PenA light pen may be connected to the signal LPSTB. This also causes the systemVIA to generate an IRQ (if enabled). It also causes the 6845 CRTC to latch theaddress of the currently selected video data byte. This may not be the same asthe displayed byte and some software correction may be necessary. Factors suchas phosphor characteristics, light pen response and the angle at which the penis used, may all affect the correction needed.2MHz External I/OTwo peripheral devices operate at 2MHz. These are the external second processorconnection and the ECONET connection.External Second ProcessorThis interface has a buffered data bus via the Peripheral Bus Controller(PBC). TheEXbus on this component provides for good data set up and hold times. Togetherwith a limited degree of line matching, this ensures reliable high speed datatransfer.PAGE: 18 with unspecified cable lengths. A maximum cable length of one metre issuggested to prevent noise problems.The interface operates at 2MHz. This means that if a 1 MHz bus peripheral isalso connected, then the address and data buses on this connector will appearto perform both 1 and 2MHz cycles.The connections are:-DO to D7 Data Bus CMOS levelsAO to A7 Address Bus TTL levelsIRQ Interrupt Request Open collector TTL levelsnTUBE Parasite chip select TTL levelsSupply +5VGround 0VPAGE: 192 CIRCUIT DESCRIPTIONThis chapter should be read in conjunction with the circuit diagram at therear of this manual.The microprocessor used in the Master 128 is a 65SC12 running at either one ortwo megahertz clock rate. Most processing is done at 2MHz, including accessesto the Random Access Memory and Read-Only Memory. The processor slows downto 1MHz when addressing slow devices such as the 1MHz Extension Bus, theAnalogue to Digital converter and the Versatile Interface. A 16MHz crystaloscillator provides clock signals for the microprocessor in conjunction withdivider circuitry on the video es backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&F0 Relative BEQ aa 2 2** Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 224BITFlags: N M7, V M6, ZTest Bits in Memory with AccumulatorOperationA AND M, N=M7, V=M8DescriptionThis instruction is used to test whether various bits are set in a memorylocation by performing an AND instruction. It does not however effecteither the accumulator of the memory location, but just sets the statusflags. Also bits 7 and 6 are transferred to the N and V flags respectively.Op. Code Addressing Mode Assembly Lang Bytes Cycles&89* Immediate* BIT #dd 2 2&24 Zero Page BIT aa 2 3&34* Zero Page,X* BIT aa,X 2 4&2C Absolute BIT aaaa 3 4&3C* Absolute,X* BIT aaaa,X 3 4* New op.codes for 65C12 only, which isfitted in the Master.PAGE: 225BMIBranch on Result MinusOperationBranch on Negative Flag=1DescriptionIf the negative flag is set this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&30 Relative BMI aa 2 2** Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 226BNEBranch on Result Not Equal to ZeroOperationBranch on Zero Flag=0DescriptionIf the zero flag is clear this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&D0 Relative BNE aa 2 2** Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 227BPLBranch on Result PlusOperationBranch on Negative Flag=0DescriptionIf the negative flag is zero this instruction performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&10 Relative BPL aa 2 2** Add 1 Cycle if page is crossedadd 2 cycle if branch crossed a page boundaryPAGE: 228BRABranch AlwaysOperationBranch AlwaysDescriptionThis instruction always performs a relative jump forwardsor backwards a specific number of bytes from the next instruction. Thisrelative figure is a two's complement signed number which can span upto 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&80 Relative BRA aa 2 3** Add 1 Cycle if page is crossedPAGE: 229BRKFlags: B 1, I 1Force BreakOperationPush PC+2 and P on stack and PC=&FFEEDescriptionThis instruction forces a break which causes the program counter to bepushed onto the stack along with the status register. The programcounter is then set to &FFFE. The BRK instruction is usually used forerrors.Op. Code Addressing Mode Assembly Lang Bytes Cycles&00 Implied BRK 1 7PAGE: 230BVCBranch on Overflow ClearOperationBranch on Overflow Flag=0DescriptionIf the overflow flag is clear this instruction performs a relative jumpforwards or backwards a specific number of bytes from the nextinstruction. This relative figure is a two's complement signed numberwhich can span up to 127 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&50 Relative BVC aa 2 2** Add 1 Cycle if branch occursadd 2 cycle if branch crossed a page boundaryPAGE: 231BVSBranch on Overflow SetOperationBranch on Overflow Flag=1DescriptionIf the overflow flag is set this instruction performs a relative jumpforwards or backwards a specific number of bytes from the nextinstruction. This relative figure is a two's complement signed numberwhich can span up to 1processor (VIDPROC) uncommitted logic arraychip (IC42) which produces 8, 4, 2 and 1 MHz signals.Random Access Memory on the microcomputer is provided by four 4464 dynamicmemory devices (ICs 17,18,23,26). Row-address and column address strobesignals for these RAMs are generated from the 8, 4 and 2MHz clock signals.These RAMs are cycled constantly at 4MHz. Two devices may have control of theRAM address lines, one is the 65SC12 microprocessor and the other is the 6845cathode ay tube controller chip (IC22).The CRTC generates the raster scan signals for the video display, togetherwith the address for each memory-mapped byte of information in the RAMs whichis required to refresh the display. An MSI CRTC multiplexer (IC31 ) switchescontrol of the RAM address lines between the microprocessor and the CRTC.The 65SC12 microprocessor is particularly suitable for this kind ofapplication, because it runs from a constant clock, d2, and so itsrequirements for memory access are predictable. Every 250ns, control of theAM address lines is switched between the microprocessor and the CRTC. Thus, ina one microsecond period, the microprocessor has two RAM accesses and the CRTChas two RAM accesses.Because the CRTC generates a sequence of addresses in order to refresh thedisplay, the row address lines of the RAMs are constantly cycled. Carefuldesign of the addressing methods in each screen mode ensures that the dynamicRAMs are also refreshed by the sequential CRTC accesses.Using this technique, two bytes of information are available per microsecondfor refreshing the raster scanned video display. With each horizontal linehaving a period of 64ms, a 40ms active display area is usual. Thus, 640 bitsof information per horizontal line are produced from the memory-mappeddisplay. The video processor VIDPROC (IC42) is a custom uncommitted logicarray developed by Acorn. At the end of each CRTC 250ns access period, itlatches the byte from thePAGE: 20RAM and, according to the display mode in operation, serialises the byte intoa one-bit stream of eight bits or a two-bit stream of four bits etc. In thisway, display modes varying from 640 pixels in 2 colours to 160 pixels in eightcolours, which may be flashing, can be produced.The video processor also contains a high speed block of static random accessmemory called a palette. This memory can be programmed to define therelationship between the logical colour produced by the RAM and the physicalcolour which will appear on the display. Thus, in a 640 pixel mode, the twocolours to appear on the display need not be black and white, they may be,say, red and blue. The information in the RAM is unchanged by the palette. itis its interpretation into physical colours which changes.Modes 0-6 in the microcomputer use software-generated characters, that is tosay, the character font to be produced on the screen is held in the memorymapped display area of the RAM and graphics or characters may be held. Thismethod of producing characters is expensive in memory, involving a minimum ofeight kilobytes for the display memory.Display Mode 7 is a Teletext mode implemented by an SAA5050 (IC32) Teletextcharacter generator. IC15 latches the information coming from the RAM prior tothe SAA5050. When using this mode, only 1 K of RAM is devoted to the displaymemory and the characters are held within it as ASCII bytes. The SAA5050 thentranslates these bytes into a standard Teletext/Prestel format display.The red, green and blue logic signals produced by the video processor arebuffered by MSl CH ROMA chip ( lC40) and fed out together with a compositesync signal to the RGB connector. This output is suitable for feeding straightto the gun drives of RGB monitors. The red, green and blue lines are summed bybinary weighted resistors to feed Q13 which produces a 1v composite videosignal suitable for feeding to monochrome monitors, on which the differentcolours will appear as different shades of grey.A modulator provides a UHF TV signal on channel 36, suitable for feeding to t27 bytes forward, or 128 bytes backward.Op. Code Addressing Mode Assembly Lang Bytes Cycles&70 Relative BVS aa 2 2** Add 1 Cycle if branch occursadd 2 cycle if branch crossed a page boundaryPAGE: 232CLC Flags: C 1Clear Carry FlagOperationCarry Flag=0DescriptionThis instruction clears the carry flag and is mainly used to prepare forADC or SBC.Op. Code Addressing Mode Assembly Lang Bytes Cycles&18 Implied CLC 1 2PAGE: 233CLD Flags: D 0Clear Decimal ModeOperationDecimal Flag=0DescriptionThis instruction switches the 65C12 back to normal binary arithmeticmode.Op. Code Addressing Mode Assembly Lang Bytes Cycles&D8 Implied CLD 1 2PAGE: 234CLI Flags: I 0Clear Interrupt Disable BitOperationInterrupt Flag=0DescriptionWhen maskable interrupts have disabled using SEI, this instructionre-enables them.Op. Code Addressing Mode Assembly Lang Bytes Cycles&58 Implied CLI 1 2PAGE: 235CLR Clear MemoryOperationM=0DescriptionCLR clears a byte of memory by storing zero at the specified location.STZ is an alternative mnemonic.Op. Code Addressing Mode Assembly Lang Bytes Cycles&64 Zero Page CLR aa 2 3&74 Zero Page,X CLR aa,X 2 4&9C Absolute CLR aaaa 3 4&9E Absolute,X CLR aaaa,X 3 5PAGE: 236CLV Flags: V 0Clear Overflow FlagOperationOverflow Flag=0DescriptionThis instruction clears the overflow flag.Op. Code Addressing Mode Assembly Lang Bytes Cycles&B8 Implied CLV 1 2PAGE: 237CMP Flags: N, Z, CCompare Memory and AccumulatorOperationA - MDescriptionCMP subtracts the contents of a memory location from the accumulatorand sets the status flags without actually affecting the contents of theaccumulator. See table below for results of compare.Op. Code Addressing Mode Assembly Lang Bytes Cycles&C9 Implied CMP #dd 2 2&C5 Zero Page CMP aa 2 3&D5 Zero Page,X CMP aa,X 2 4&D2 (Indirect Zero Page) CMP (aa) 2 5&CD Absolute CMP aaaa 3 4&DD Absolute,X CMP aaaa,X 3 4*&D9 Absolute,Y CMP aaaa,Y 3 4*&C1 (Indirect,X) CMP (aa,X) 2 6&D1 (Indirect),Y CMP (aa),Y 2 5** Add 1 Cycle if page crossedAfter a CMP instruction the following conditions will apply:AM N =0* Z = 0 C = 1* Only valid for 'two's complement' comparePAGE: 238CPX Flags: N, Z, CCompare Memory and X RegisterOperationX - MDescriptionCPX subtracts the contents of a memory location from the X registerand sets the status flags without actually affecting the contents of theX register. See table below for results of compare.Op. Code Addressing Mode Assembly Lang Bytes Cycles&E0 Immediate CPX #dd 2 2&E4 Zero Page CPX aa 2 3&EC Absolute CPX aaaa 3 4After a CPX instruction the following conditions will apply:X < M N = 1* Z = 0 C = 0X = M N = 0 Z = 1 C = 1X > M N = 0* Z = 0 C = 1* Only valid for 'two's complement' comparePAGE: 239CPY Flags: N, Z, CCompare Memory and Y RegisterOperationY - MDescriptionCPY subtracts the contents of a memory location from the Y registerand sets the status flags without actually affecting the contents of theY register. See table below for results of compare.Op. Code Addressing Mode Assembly Lang Bytes Cycles&C0 Immediate CPY #dd 2 2&C4 Zero Page CPY aa 2 3&CC Absolute CPY aaaa 3 4After a CPY instruction the following conditions will apply:Y M N =0* Z = 0 C = 1* Only valid for 'two's complement' comparePAGE: 240DEC/DEA Flags: N, ZDecrement Memory by OneOperationM = M - 1DescriptionThis instruction subtracts one from a memory location and sets theappropriate status flags. The additional addressing mode on the 65C12allows the accumulator to be decremented by using DEC A or just DEA.Op. Code Addressing Mode Assembly Lang Bytes Cycles&3A* Accumulator* DEC A(DEA) 1 2&C6 Zero Page DEC aa 2 5&D6 Zero Page,X DEC aa,X 2 6&CE Absolute DEC aaaa 3 6&DE heaerial input of a domestic television receiver. Colour is derived from a PAL(phase alternating line) encoder circuit which modulates the colourinformation on to the colour subcarrier frequency. Q10 is a 17.73MHzoscillator circuit which is divided by a ring counter (IC46) giving an outputat the colour subcarrier frequency of 4.43361875MHz which is fed to IC40. Thisselects different phases of the 'U' and 'V' signals according to whether ared, green, blue, cyan, magenta, yellow or white colour is to be produced.These signals produce the colour subcarrier signal which is added to themonochrome output from Q8 by the buffer Q9. A reference colour burst isprovided at the beginning of each line for the receiving televisionto interpret the colour information.PAGE: 21The PAL signal may be added to the 1 v video connector by the insertion of a470pF capacitor between the emitter of Q9 and the base of Q7.Resistors R132-4 adjust the luminance balance of the colours.Memory provision comprises four 4464 dynamic RAM chips (IC16, 17, 23, 26)which give 128 kilobytes of storage and a one megabit ROM ( IC24) mapped aseight 16K blocks,INPUT/output is under the control of an MSI I/O controller IC15. This isconnected directly to the control lines of the executive chips responsible forperipheral access.One 6522 VIA device (IC9) is devoted to internal system operation. Port Bdrivesan addressable latch which is used to provide read and write strobe signalsfor the speech interface, the keyboard and the sound generator chip. Alsocoming from this latch (IC 32) are control lines C0 and C1 which indicate theamount of RAM devoted to the display memory to be 16K, 8K, 10K or 20K. Pins 6and 7 of the addressable latch drive the caps lock and shift lock LEDs on thekeyboard.The rest of Port B on the internal system VIA is used to input the two 'firebutton' signals from the analogue to digital converter interface and tocontrol a real-time clock/CMOS RAM chip. Each time the system VIA is writtento, any changes on Port B which should affect the addressable latch arestrobed into the latch by a flip flop which is triggered from the 1 MHz clocksignal. Port A of the system VIA(IC9) is a slow data bus which connects tothe keyboard, the RTC/CMOS RAM chip and the sound generator. Port B is theunbuffered User Port.IC18 is a four channel sound generator chip which may be programmed to givevarying frequency and varying attenuation on each channel. An extra analogueinput from the 1 MHz extension bus is added to the sound generator signal andthen filtered by a quad operational amplifier (IC17). IC19 provides audio poweramplification to drive a speaker,Two forms of serial interface are provided, one is an audio cassette at either300 or 1200 baud and the other is RS423, over a whole range of baud rates.RS423 is electrically compatible with RS232C in most applications.)A 6850 asynchronous communications interface adaptor (IC4) is used to bufferand serialise or deserialise the data. A second ULA (SERPROC) is used in theserial interface, (IC7). Contained within this ULA is a programmable baudrate generator, a cassette data/clock separator and switching to select eitherRS423 or cassette operations. IC42 divides the main board 16MHz clock by 13and this signal is divided further within the serial interface ULA to producethe 1200 Hz cassette signal.PAGE: 22Automatic motor control of an audio cassette recorder is achieved by a smallrelay driven by a transistor from the serial interface ULA. The signal out ofthe cassette is buffered and the incoming signal is suitably filtered andshaped by a three stage amplifier. This is a quad operational amplifier(IC35). The RS423 data in and out signals and request-to-send andclear-to-send signals are interfaced by ICs 74 and 75 which translate betweenTTL and standard RS423/232 signal levels. This is one of the few sections ofcircuitry on the Microcomputer which requires an additional -5v supply to bepresent.A four-channel analogue to digital converter facility is prAbsolute,X DEC aaaa,X 3 7* New op.codes for 65C12 only, which isFitted to the Master.PAGE: 241DEX Flags: N, ZDecrement X Register by OneOperationX = X - 1DescriptionThis instruction subtracts one from the X register and sets theappropriate status flags.Op. Code Addressing Mode Assembly Lang Bytes Cycles&CA Implied DEX 1 2PAGE: 242DEY Flags: N, ZDecrement X Register by OneOperationY = Y - 1DescriptionThis instruction subtracts one from the X register and sets theappropriate status flags.Op. Code Addressing Mode Assembly Lang Bytes Cycles&88 Implied DEY 1 2PAGE: 243EOR Flags: N, ZDecrement X Register by OneOperationA = A EOR MDescriptionThis instruction performs an exclusive OR between the accumulator and amemory location leaving the result in the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&49 Immediate EOR #dd 2 2&45 Zero Page EOR aa 2 3&55 Zero Page,X EOR aa,X 2 4&52 (Indirect Zero Page) EOR (aa) 2 5&4D Absolute EOR aaaa 3 4&5D Absolute,X EOR aaaa,X 3 4*&59 Absolute,Y EOR aaaa,Y 3 4*&41 (Indirect,X) EOR (aa,X) 2 6&51 (Indirect),Y EOR (aa),Y 2 5** Add 1 cycle if page crossedPAGE: 244INC/INA Flags: N, ZIncrement Memory by OneOperationM = M + 1DescriptionThis instruction adds one to a memory location and sets theappropriate status flags. The additional addressing mode on the 65C12allows the accumulator to be incremented by using INC A or just INAOp. Code Addressing Mode Assembly Lang Bytes Cycles&1A* Accumulator* INC A(INA) 1 2&E6 Zero Page INC aa 2 5&F6 Zero Page,X INC aa,X 2 6&EE Absolute INC aaaa 3 6&FE Absolute,X INC aaaa,X 3 7* New op.codes for the 65C12which is fitted to the MasterPAGE: 245INX Flags: N, ZIncrement X Register by OneOperationX = X + 1DescriptionThis instruction adds one to the X register and sets theappropriate status flags.Op. Code Addressing Mode Assembly Lang Bytes Cycles&E8 Implied INX 1 2PAGE: 246INY Flags: N, ZIncrement Y Register by OneOperationY = Y + 1DescriptionThis instruction adds one to the Y register and sets theappropriate status flags.Op. Code Addressing Mode Assembly Lang Bytes Cycles&C8 Implied INY 1 2PAGE: 247JMP Jump to New LocationOperationPC = new locationDescriptionThis instruction jumps to the new location by loading the newaddress to the program counter.Op. Code Addressing Mode Assembly Lang Bytes Cycles&4C Absolute JMP aaaa 3 3&6C (Indirect) JMP (aaaa) 3 5&7C (Indirect,X) JMP (aa,X) 3 6PAGE: 248JSR Jump to SubroutineOperationPush PC+2 on stack then PC = new locationDescriptionThis instruction is similar to JMP but first pushes the current programcounter plus 2 onto the stack. When a RTS instruction is encounteredthe program counter is then reset using the location that was previouslystored on the stack.Op. Code Addressing Mode Assembly Lang Bytes Cycles&20 Absolute JSR aaaa 3 6PAGE: 249LDA Flags: N, ZLoad Accumulator with MemoryOperationA = MDescriptionThis instruction loads the accumulator with the contents of a specifiedbyte of memory.Op. Code Addressing Mode Assembly Lang Bytes Cycles&&A9 Immediate LDA #dd 2 2&A5 Zero Page LDA aa 2 3&B5 Zero Page,X LDA aa,X 2 4&B2 (Indirect Zero Page) LDA (aa) 2 5&AD Absolute LDA aaaa 3 4&BD Absolute,X LDA aaaa,X 3 4*&B9 Absolute,Y LDA aaaa,Y 3 4*&A1 (Indirect,X) LDA (aa,X) 2 6&B1 (Indirect),Y LDA (aa),Y 2 5** Add one cycle if page crossedPAGE: 250LDX Flags: N, ZLoad X Register with MemoryOperationX = MDescriptionThis instruction loads the X register with the contents of a specifiedbyte of memory.Op. Code Addressing Mode Assembly Lang Bytes Cycles&A2 Immediate LDX #dd 2 2&A6 Zero Page LDX aa 2 3&B6 Zero Page,Y LDX aa,Y 2 4&AE Absolute LDX aaaa 3 4&BE Absolute,Y LDX aaaa,Y 3 4** Add one cycle if page crossedPAGE: 251LDY Flags: N, ZLoad Y Register with MemoryOperationY + MDescriptionThis ovided by a mPD7002IC73. This device connects straight to the microcomputer's data bus and it is adual slope converter with its voltage reference being provided by the threediodes, D6, D7 and D8.Connection is made to the ECONET by a five way DIN connector mounted on themain circuit board. The interface electronics including the 68B54, linedrivers, receivers and chatter disconnect components are mounted on a separatecircuit board. This board has two connectors:-a) A 5-way connector which has a one-to-one connection with the DIN connector.b) A15-way connector provides the CPU data bus together with address, timing reference, chip select and interrupt signals. The main PCB has two further address connections for future expansion.A 6854 Advanced Data Link Controller circuit handles the Econet protocol. Datato be transmitted onto the network is fed from the ADLC to the line drivercircuit which produces a differential signal drive to the Econet cables.Received data is detected and converted to a logic signal by one half of IC94which is a dual compare circuit type LM319. The received data is then fed backto the data link controller circuit.An Econet installation has a external master clock station which controls thetiming for the network. This clock signal is transmitted around the network asa second differential line signal and it is used to clock the data in and outof the data link controller circuits. The network clock is also detected usingone half of the LM319 comparator IC4 and the detected clock is then fed to bothreceive clock and transmit clock inputs on the 6854. In the presence of anetwork clock, the monostable circuit, IC2 is permanently triggered and thisprovides a data carrier detect signal for the data link controller chip. Oncethe network clock is removed, the monostable immediately drops out and thedata carrier is no longer detected.Econet is a broadcast network system on which a number of stations may attemptto transmit their data over the network at any given time. In this case, acollision can occur. the transmitting station detects the collision and backsoff before attempting to try again to transmit over the network. Collisionarbitration software isPAGE: 23included in the Econet system. Collisions on the network data lines result inthe differential signal on the two data wires being reduced and this conditionis detected by IC95 which is another dual comparator circuit.When there is a good differential data signal on the network one output ofIC95 or the other will be low, in which case the output of IC91 Pin 6 will behigh, indicating no collision. When there are no collisions on the network,and the network clock is detected by the clock monostable, the data linkcontroller is clear to send data over the network.When there is a collision on the network both outputs of IC91 will go high andthe clear to send condition will cease. Note that when the computer is notconnected to the network a collision-like situation results, in which caseagain the data link controller will not get a clear to send condition.Each Econet system requires termination at the two extreme ends of the networkwith network terminator boxes. It also requires an external network clock box.The network clock generates a 6MHz signal which is divided by two to produce3MHz and other clock rates down to 75KHz. The setting of this clock signaldepends on the length of the network, with the longer networks requiring aslower clock.Up to 255 stations may be connected to each Econet with each station beingidentified by a unique station identification number. This station ID isprogrammed into the battery-backed CMOS RAM. The data link controller circuitproduces interrupts which are fed to the central processor NMI line. Theseinterrupts are enabled every time the station ID is read. Once in the datalink controller interrupt service routine the DTR output of the ADLC goes lowin order to remove the interrupt.IC78 is a WD1770 or WD1772 floppy disc drive controller circuit which is usedinstruction loads the Y register with the contents of a specifiedbyte of memory.Op. Code Addressing Mode Assembly Lang Bytes Cycles&A0 Immediate LDX #dd 2 2&A4 Zero Page LDX aa 2 3&B4 Zero Page,X LDX aa,X 2 4&AC Absolute LDX aaaa 3 4&BC Absolute,X LDX aaaa,X 3 4** Add 1 cycle if page crossedPAGE: 252LSR Flags: N 0, Z, CLogical Shift RightOperationC = M0, M = M/2DescriptionShift the contents of a memory location or the accumulator one bit to theright. This operation effectively divides by two and leaves any remainderin the carry flagOp. Code Addressing Mode Assembly Lang Bytes Cycles&4A Accumulator LSR A 1 2&46 Zero Page LSR aa 2 5&56 Zero Page,X LSR aa,X 2 6&4E Absolute LSR aaaa 3 6&5E Absolute,X LSR aaaa,X 3 7PAGE: 253NOP No OperationOperationNo operationDescriptionThis is an instruction which has no effect other than to use up a memorylocation and takes 2 cycles. It may be used to reserve space or to replaceredundant code without having to re-assemble.Op. Code Addressing Mode Assembly Lang Bytes Cycles&EA Implied NOP 1 2PAGE: 254ORA Flags: N, ZOR Memory with AccumulatorOperationA = A OR MDescriptionA logical OR is performed between the accumulator and a memorylocation. The result is then left in the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&09 Immediate ORA #dd 2 2&05 Zero Page ORA aa 2 3&15 Zero Page,X ORA aa,x 2 4&12 (Indirect Zero Page) ORA (aa) 2 5&0D Absolute ORA aaaa 3 4&1D Absolute,X ORA aaaa,X 3 4*&19 Absolute,Y ORA aaaa,Y 3 4*&01 (Indirect,X) ORA (aa,X) 2 6&11 (Indirect),Y ORA (aa),Y 2 5** Add 1 cycle if page crossedPAGE: 255PHA Push Accumulator onto StackOperationPush ADescriptionThis instruction pushes the contents of the accumulator onto the stack.Op. Code Addressing Mode Assembly Lang Bytes Cycles&48 Implied PHA 1 3PAGE: 256PHP Push Processor Status onto StackOperationPush Status register (P)DescriptionThis instruction pushes the contents of the status register onto the stack.Op. Code Addressing Mode Assembly Lang Bytes Cycles&08 Implied PHP 1 3PAGE: 257PHX Push X Register onto StackOperationPush X registerDescriptionThis instruction pushes the contents of the X register onto the stack.Op. Code Addressing Mode Assembly Lang Bytes Cycles&DA Implied PHX 1 3PAGE: 258PHY Push Y Register onto StackOperationPush Y registerDescriptionThis instruction pushes the contents of the accumulator onto the stack..Op. Code Addressing Mode Assembly Lang Bytes Cycles&5A Implied PHY 1 3PAGE: 259PLA Flags: N, ZPull Accumulator from StackOperationPull AccumulatorDescriptionThis instruction pulls a value from the stack into the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&68 Implied PLA 1 4PAGE: 260PLP Flags: N, V, B, D, I, Z, CPull Processor Status from StackOperationPull Status register (P)DescriptionThis instruction pulls a value from the stack into the status register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&28 Implied PLP 1 4PAGE: 261PLX Flags: N, ZPull X Register from StackOperationPull X RegisterDescriptionThis instruction pulls a value from the stack into the X register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&FA Implied PLX 1 2PAGE: 262PLY Flags: N, ZPull Y Register from StackOperationPull Y registerDescriptionThis instruction pulls a value from the stack into the Y register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&7A Implied PLY 1 2PAGE: 263ROL Flags: N, Z, CRotate LeftOperationC = M7, M = M * 2, M0 = CDescriptionRotate the contents of a memory location or the accumulator one bit tothe left.Op. Code Addressing Mode Assembly Lang Bytes Cycles&2A Accumulator ROL A 1 2&26 Zero Page ROL aa 2 5&36 Zero Page,X ROL aa,X 2 6&2E Absolute ROL aaaa 3 6&3E Absolute,X ROL aaaa,X 3 7PAGE: 264ROR Flags: N, to interface to one or two single or double sided 5 or 8 inch floppy discdrives. Logic signals from the controller to the disc drive are buffered byIC1. The incoming signal from the disc drive is first conditioned bymonostable IC87 producing a pulse train with each pulse of fixed width. Thesepulses are then fed to the data separation circuits ICs 81 and 82. This is adigital monostable. IC86 divides the 8MHz clock signal down to 31.25 KHz. ICs83, 84 and 85 are then used to detect index pulses coming in from the drivewhich show that the drive is ready for a read or write operation.IC69 is a versatile interface adaptor. Port A is used to provide a centronicsstandard parallel printer interface, with the octal buffer IC70 being used tobuffer the data lines. Port B is left uncommitted and is free for use by theuser for input or output purposes.PAGE: 24The address and data lines A0-A7 and D0-D7, together with some page selectlines are available as the 1 MHz extension bus to which various peripheraldevices, such as Teletext interface, may be connected. All accesses to thisbus will be at 1 MHz processor speed. The octal buffer DXXXXXXX and the octaltransceiver DXXXXXXX are used to interface these signals to the internal dataaddress bus.Selected address and data lines are available on the Tube connector which isused to connect second language processors into the system.KeyboardNinety-three keys are provided, ninety-two of which are in a modified 8x13matrix. A keyboard encoder, KBDENC (IC16) is used to scan the keyboard. Duringidle (free run) mode, pressing any key will cause an IRQ to be generated viathe system 6522. A connection is provided from IC16 to a 6522 'CA' typeconnection. Hence the interrupts thus generated are controlled by the 6522control register.Depression of either of the shift keys, or the control key does not generatean interrupt.The power supply unit produces 5 volts at around 2 amps and -5 volts at around50mA for use on the main circuit board. Auxiliary power for accessories isavailable on an external connector.DETAILED CIRCUIT OPERATIONIn this section, certain parts of the circuit will be described.Pins 4, 5, 6, and 7 of the video processor (IC6) produce 1, 2, 4 and 8MHzclocks in phase. A D-type flip flop (half of IC34) divides the 2M Hz clocksignal in order to produce the system 1 MHz clock. A 2MHz signal of suitablephase is produced at the output of another D-type (half of IC30) and this isfurther clocked through the second D-type (half of IC30), and via an OR gateproducing the normal 2MHz clock input to the microprocessor. Requests for a 1MHz processor cycle from the address decoding are fed via an inverter (1/6thof IC33) to the D-type (half of IC30) which remembers that a 1 MHz cycle hasbeen requested.At the appropriate time, as governed by the 2M Hz clock, one of the 2MHz clockcycles is marked off by the D-type (half of IC34) and when this happens theD-type that remembered that a request had been made is cleared.A 6MHz clock signal is required for the Teletext character generator (IC32).This signal is produced by knocking a reset flip flop (two quarters of IC40)backwards and forwards from 8MHz and 4MHz clock signals. The resulting flipflop output is then itself inverted according to the state of the 2M Hz clocksignal by an exclusive OR gate (of IC38). Glitches on this output are removedby R119 and C48 toPAGE: 25produce the 6MHz clock signal at Pin B of IC37.The dynamic RAMs are constantly cycled by a row address strobe signal which isproduced by a D-type connected to the 8 and 4MHz clock signals (half of lC44).This RAS signal then drives all of the dynamic RAMs via R106. The dynamic RAMsare divided into two banks of 16 kilobytes, that is two banks of 8 RAMs. Thesebanks are input- or output-enabled by virtue of having their column addressstrobe available. In Model A computers with only one bank of RAM only CAS 1 isused. 32-kilobyte computers have a second bank of RAMs selected by a 74L551circuit (IC28) which controls the 74S13Z, CRotate RightOperationC = M0, M = M / 2, M7 = CDescriptionRotate the contents of a memory location or the accumulator one bit tothe right.Op. Code Addressing Mode Assembly Lang Bytes Cycles&6A Accumulator ROR A 1 2&66 Zero Page ROR aa 2 5&76 Zero Page,X ROR aa,X 2 6&6E Absolute ROR aaaa 3 6&7E Absolute,X ROR aaaa,X 3 7PAGE: 265RTI Flags: N, V, B, D, I, Z, CReturn from InterruptOperationPull Status register (P) then pull program counter (PC).DescriptionThis instruction pulls both P and PC from the stack on return from aninterrupt.Op. Code Addressing Mode Assembly Lang Bytes Cycles&40 Implied RTI 1 6PAGE: 266RTS Return from SubroutineOperationPull Program counter (PC) from stackDescriptionThis instruction is used in conjunction with JSR to terminate a subroutine.RTS pulls into the program counter the values pushed by JSR from thestack. Execution is then resumed just after the original JSR.Op. Code Addressing Mode Assembly Lang Bytes Cycles&60 Implied RTS 1 6PAGE: 267SBC Flags: N, V, Z, CSubtract from Accumulator with CarryOperationA,C = A - M - (1-C)DescriptionThis subtracts the contents of a memory location from the accumulator.The carry flag is used as a borrow and is usually set before a subtraction.When the carry flag is clear 1 is also taken away, thus allowing multiplebyte subtraction.Op. Code Addressing Mode Assembly Lang Bytes Cycles&E9 Immediate SBC #dd 2 2&E5 Zero Page SBC aa 2 3&F5 Zero Page,X SBC aa,X 2 4&F2 (Indirect Zero Page) SBC (aa) 2 5&ED Absolute SBC aaaa 3 4&FD Absolute,X SBC aaaa,X 3 4*&F9 Absolute,Y SBC aaaa,Y 3 4*&E1 (Indirect,X) SBC (aa,X) 2 6&F1 (Indirect),Y SBC (aa),Y 2 5*PAGE: 268SEC Flags: C 1Set Carry FlagOperationCarry flag = 1DescriptionThis instruction sets the carry flag and is mainly used to prepare for SBCor ADC.Op. Code Addressing Mode Assembly Lang Bytes Cycles&38 Implied SEC 1 2PAGE: 269SED Flags: D 1Set Decimal ModeOperationDecimal flag = 0DescriptionThis instruction switches the 65C12 to binary coded decimal arithmeticmode.Op. Code Addressing Mode Assembly Lang Bytes Cycles&F8 Implied SED 1 2PAGE: 270SEI Flags: I 1Set Interrupt Disable StatusOperationInterrupt flag = 1DescriptionThis instruction disables maskable interrupts by setting the interrupt flag.While all normal MOS functions will be suspended until a CLI isperformed.Op. Code Addressing Mode Assembly Lang Bytes Cycles&78 Implied SEI 1 2PAGE: 271STA Store Accumulator in MemoryOperationM = ADescriptionThis instruction stores the accumulators contents to a specified memorylocation.Op. Code Addressing Mode Assembly Lang Bytes Cycles&85 Zero Page STA aa 2 3&95 Zero Page,X STA aa,X 2 4&92 (Indirect Zero Page) STA (aa) 2 6&8D Absolute STA aaaa 3 4&9D Absolute,X STA aaaa,X 3 5&99 Absolute,Y STA aaaa,Y 3 5&81 (Indirect,X) STA (aa,X) 2 6&91 (Indirect),Y STA (aa),Y 2 6PAGE: 272STX Store X Register in MemoryOperationM = XDescriptionThis instruction stores the X register in a specified memorylocation.Op. Code Addressing Mode Assembly Lang Bytes Cycles&86 Zero Page STX aa 2 3&96 Zero Page,Y STX aa,Y 2 4&8E Absolute STX aaaa 3 4PAGE: 273STX Store Y Register in MemoryOperationM = YDescriptionThis instruction stores the Y register in a specified memorylocation.Op. Code Addressing Mode Assembly Lang Bytes Cycles&84 Zero Page STY aa 2 3&94 Zero Page,X STY aa,X 2 4&8C Absolute STY aaaa 3 4PAGE: 274STZ Clear MemoryOperationM = 0DescriptionSTZ clears a byte of memory by storing zero at the specified location.CLR is an alternative mnemonic.Op. Code Addressing Mode Assembly Lang Bytes Cycles&64 Zero Page STZ aa 2 3&74 Zero Page,X STZ aa,Y 2 4&9C Absolute STZ aaaa 3 4&9E Absolute,X STZ aaaa,X 3 4** Add 1 cycle if page crossedPAGE: 275TAX Flags: N, ZTransfer Accumulator to X RegisterOperationX = ADescriptionThis 9 (half of IC45) producing the CASsignals. The other half of 74S139 (half of IC45) is used to select between theprocessor and CRT address lines.The video processor uncommitted logic array takes data bytes from the RAM atthe rate of sixteen bits per microsecond and then serialises them according tothe display mode required. The bit streams for serialisation are then fedthrough a block of high speed palette RAM which relates the logical colourfrom the serialiser to the physical colour to be produced on the display. Thepalette drive is 16x4 bits with the four bits representing red, green and bluedrives, together with a flash bit. The data bus input to the video processoris also used to access the mode control register when the device is chipselected. In the Teletext display mode, RGB information is fed straight intothe video processor from the SAA5050 for the cursor control to be added.VDU throughput is much enhanced by the use of hardware scroll. A register inthe CRTC is used to store the start of screen address in the screen memory.Thus, in order to scroll the screen, it is only necessary to increment thisregister by the number of characters per line and then write to the memoryaddress where the last screen data was and where the new screen line data nowneeds to go.The number of address lines from the CRTC used to address the screen memoryhas to be sufficient to cater for the biggest screen, which is 20 kilobytes,therefore, sufficient addresses to satisfy 32 kilobytes of screen memory areused. By the hardware scrolling technique the picture rolls around in 32kilobytes. Forexample, with a scroll of eight kilobytes in a 20kilobyte screen, the originalstart of screen for the 20 kilobyte mode was &3000. After the eight kilobytescroll, the current start of screen address is &5000 with the end of the screenas viewed by the CRTC at &5000 plus 20 kilobytes, that is &A000.The address &A000 is not physically in the RAM and it is therefore necessary tomodify this address in order to move it to the original start of the screen.This is done by adding 12 kilobytes to get the required physical address. Inthis way, the physical memory addresses are kept within the required range.For the different screen modes we need to add different numbers as their startof screen addresses are different.PAGE: 26The following table shows this:-Modes Screen Size Start of Screen Address Number to be added0,1,2 20K &3000 12K3 16K &4000 16K4,5 10K &5000 (or &1800) 22K6 8K &6000 (or &2000) 24KThe number to be added to the start screen address in order to keep thehardware scrolling within the correct physical memory address range is definedby the control lines CO and C1 from 74LS5259 (IC32). This number is thencomputed with the result being added to the higher CRTC refresh address linesby the CTRC multiplexer (IC31 ).PAGE: 273 MEMORY ORGANISATIONOperation of the RAM and ROM is controlled by the Memory Controller integratedcircuit. The principal function of this device is to control the memory paging.Memory MapThe 65C12 can directly address 64K locations. As over 1/2 Mbyte may beresident, a paging scheme is implemented. &FFFF ROM &FF00 } I/O or ROM } MemoryMapped I/0 &FE00 } ROM &E000 ROM/RAM (Region b) &C000 ROM/Sideways RAM &9000 ROM/RAM &8000 ROM/RAM (Region a) &3000 RAM &0000 Machine Memory MapThe current memory map is dictated by the contents of the two latches. ROMSELect and ACCess CONtrol located at &FE30 and &FE34 respectively. Thecontents of these two latches are:- d7 d6 d5 d4 d3 d2 d1 d0(&FE30)RAM 0 0 0 PM3 PM2 PM1 PM0(&FE34)IRR TST IFJ ITU Y X E DThe contents of ROMSEL dictate the selection of memory which resides from&8000 to &BFFF.PAGE: 28The contents of ACCON principally dictate the activity of two regions ofmemory. (a) &3000 to &7FFF (b) &C000 to &DFFFRandom-Access MemoryRAM is functionally split up into two regions. The main region supports thelinstruction copies the contents of the accumulator to the X register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&AA Implied TAX 1 2PAGE: 276TAY Flags: N, ZTransfer Accumulator to Y RegisterOperationY = ADescriptionThis instruction copies the contents of the accumulator to the Y register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&A8 Implied TAY 1 2PAGE: 277TRB Flags: ZTest and Reset BitsOperationM = (A EOR &FF) AND MDescriptionThis instruction ANDs the complement of the accumulator with thespecified memory location and stores the result in that location. The Zflag is set if A AND M = 0.Op. Code Addressing Mode Assembly Lang Bytes Cycles&14 Zero Page TRB aa 2 5&1C Absolute TRB aaaa 3 6PAGE: 278TSB Flags: ZTest and Set BitsOperationM = A OR MDescriptionThis instruction ORs the accumulator with the specified memory locationand stores the result in that location. The Z flag is set ifA AND M = 0.Op. Code Addressing Mode Assembly Lang Bytes Cycles&04 Zero Page TSB aa 2 5&0C Absolute TSB aaaa 3 6PAGE: 279TSX Flags: N, ZTransfer Stack Pointer to X RegisterOperationX = Stack pointer (S)DescriptionThis instruction copies the contents of the stack pointer to the X register.Op. Code Addressing Mode Assembly Lang Bytes Cycles&BA Implied TSX 1 2PAGE: 280TXA Flags: N, ZTransfer X Register to AccumulatorOperationA = XDescriptionThis instruction copies the contents of the X register to the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&8A Implied TXA 1 2PAGE: 281TXS Transfer X Register to Stack PointerOperationStack pointer (S) = XDescriptionThis instruction copies the contents of the X register to the stack pointer.Op. Code Addressing Mode Assembly Lang Bytes Cycles&9A Implied TXS 1 2PAGE: 282TYA Flags: N, ZTransfer Index Y to AccumulatorOperationA = YDescriptionThis instruction copies the contents of the X register to the accumulator.Op. Code Addressing Mode Assembly Lang Bytes Cycles&98 Implied TYA 1 2PAGE: 283INDEXA-to-D converter, 17AC Parametric test (peripheral bus), 65Access Control (ACCCON), 27Access restrictions RTCRAM, 35Acorn approval, 72ADC, 216Address space allocation, 73Address space map, 77ADFS track format, 146ADVAL (Master Compact), 199Advanced Network Filing System, 148Alarm,34Analogue port, 17Analogue to Digital converter, 17AND, 217ANDY, 30ANFS, 148ANFS and NFS, differences, 200ANFS configuration, 33ANFS enhancements, 154ANFS Error messages, 155ANFS OS commands, 149ANFS Printing, 154ANFS/DFS compatibility, 157ANFS/NFS, routines to check which, 159APC sequence, 160Approval of equipment by Acorn, 72Architecture, 12Aries B32 Shadow RAM, compatibility, 170ASL, 218Audio Generator, 14, 33Automatic motor control, 22AUTO, 204Auxiliary control register (User VIA), 56B Bus drive waveforms, 68Base processor, 12BASIC 4 changes from earlier versions, 203Baud rate generator, 61BBC Micro Expansion Box, 74BBR (Rockwell 65C02 only), 219BBS (Rockwell 65C02 only), 220BCC, 221BCS, 222BEQ, 223BIT 224BMI, 225BNE, 226Bootstrapping (AN FS) , 157BPL, 227BRA (65C12 only), 228Bridges (ANFS), 158BRK instruction, 88, 229Buffer transfer (Editor/Language), 161Buffers, ANFS, 148BVC, 230BVS, 231C Bus drive waveforms, 67Cartridge interface, 210Cartridge pinout, Master 128, 211Cartridge ROM, 30Cartridge sockets, 189Changes between : BASIC 4 and earlier versions, 203 NFS to ANFS, 200 Master 128 and B/B+, 171 , Master 128 and Compact, 190 Master 128 memory map from B/B+, 186Changes: Model B+ and Model B, 165Character definitions (memory), 83Circuit description, 19Circuit operation detail, 24CLC, 232CLD, 233CLI (mnemonic), 234CLI buffer, 83Clock, 15Clock rate, CPU, 19Clock signals, 24CLR (65C12 only), 235CLV,236CMOS RAM, 15CMOS RAM byte allocation, 33CMP,237CNPV 94CODE key (Master Compact), 197Column detection mode (keyboard), 39Compact, 190Comparison of memory mapanguage workspaces, buffers etc. and provides the bit-mapped screen. Thesecond region provides four 16K 'Sideways' RAM segments. These are link-selected into ROM locations 4,5,6 and 7. They may be deselected, reinstatingthe ROM sockets in blocks of 32 Kbytes.Within the main 64 Kbyte region, the lower 32K is used within the &0000 to&7FFF region of the CPU memory map. The 64K of DRAM is distributed as follows:- ----------------------------- Bits in ACCON &FFFF &7FFF With E or X active &B000 &3000 t --------------------------------------------- &DFFF s WithRam Y active CPUAddress &9000 &C000 t ADDRESS -------------------------------------------- &888F s RAM active &8000 ------------------------------------------- &8000 t &0000 ------------------------------------------ &0000 Summary of RAM memory mapThe upper 32K is split up into three, self-contiguous regions. The largestportion of this is a 20Kbyte region designated LYNNE. This can be overlayed onthe region (a) of main memory.When bit D in ACCCON is set, the CRT controller will display the contents ofLYNNE. When bit D is cleared, the region (a) of main memory will be displayed.PAGE: 29When bit E in ACCCON is set, if the address range is &3000 to &7FFF the CPUwill read/write Lynne:1. Wait until end of cycle2. Was the last cycle an opcode fetch (sync=1) From &C000 to &DFFF in RAM?Yes - go to 3No go to 43. Is this Cycle an opcode fetch?Yes go to 4No go to 54. Access main memory. Go to 15. Write Lynne. Go to 1This system allows for the screen bit map to be removed from the main CPUmemory map of which it occupies a significant proportion. It will, however,only work if the screen is being accessed by opcodes from a known region -i.e. the MOS VDU drivers.A mechanism is also provided to permit 'illegal' screen access. Bit X inACCCON, when set, causes all accesses to region (a) to be re-directed to LYNNE.This occurs irrespective of the opcode address, hence considerable care must beexercised in its use. When cleared the memory map returns to its usual format.In the same way that the BASIC variable HIMEM will always have the value &8000when LYNNE is used, it is desirable for the variable PAGE to have the value&E00, irrespective of the current filing system. This is achieved by providinga filing system workspace. Bit Y in ACCCON when set, causes 8Kbyte of RAM,referred to as HAZEL, to be overlayed on the MOS VDU drivers, i.e. from &C000to &DFFF. When this bit has been set, no calls may be made to the MOS for VDUoperation. The code which performs this paging operation is responsible forresetting the Y bit, as no hardware is provided for this purpose.The remaining bits in ACCCON are used to control various peripheral systems.ITU, when set, enables the CPU to access the internal second processorrather than the external one.IRR is InterRupt Request. When set, this bit causes an open drain output topull the CPU NlRQ pin down to Vss.PAGE: 30ROMSELThe contents of ROMSEL determine the paging of memory in the 16K region &8000to &BFFF. One of sixteen 16Kbyte ROM memory segments may be selected. Oneadditional 4Kbyte RAM segment may be selected from &8000 to &8FFF.Eight of the segments are assumed to be in four 32Kbyte ROMs where the leastsignificant bit of ROMSEL selects between the upper and lower segments. Sevenof the segments exist together with a ROM which is active from &C000 to &FFFFwithin a 128Kbyte ROM. This ROM is connected via a separate data bus. The four32Kbyte devices and one 16Kbyte device are connected in a matrixing scheme. Segments 8 7,6 5,4 Chip Selects o o o or RAM enablingOutput o-----------------------------------EnableCartridge o----------------------------------ROMsChip Select o o Segments 3,2 1,0In this way, fewer connections to the controller logi (M128 & B/B+), 186Compatibility ANFS/DFS, 157Composite video, 44Control registers, video, 45Controller chip, CRT, 46Controller, keyboard, 37Controller, Peripheral Bus, 63Co-processor (80186), 131CP/M, 123CP/M character I/O, 126CP/M device assignments, 126CP/M device characteristics, 129CP/M disc format, 147CP/M IOBYTE facility, 127CP/M logical devices, 128CP/M physical devices (Acorn), 128CP/M screen control, 125CP/M System patch area, 130CP/M Terminal Emulator codes, 125CPX, 238CPY, 239Cathode Ray Tube Controller chip, 46CRTC chip registers, 47CRTC Multiplexer, 48Data Bus (Slow), 32Data register (User VIA), 53DEA/DEC A (65C12 only), 240DEC, 240Detailed circuit operation, 24DEX, 241DEY 242DFS (B+), 169DFS track format, 145DFS/ANFS compatibility, 157Differences between : NFS and ANFS, 200 Master 128 & B/B+ , 171 Master 128 & Compact, 190 Model B+ and Model B, 165Disc Filing Systems, 145Display, 42DRAM, 12DRAM timing, 31Dual Processor Systems, 98Dynamic RAM chip (4464), 19Dynamic RAM timing, 31E Bus drive waveforms, 69ECONET, 22Econet terminal, 185Editor (Master 128), 161, 183EDIT, 204EEPROM (Master Compact), 194EOR, 243Equipment approval by Acorn, 72Error messages, ANFS, 155Error messages, extended in ANFS, 202Events on reception (ANFS), 159Events (Z80), 121EVENTV,87, 96Expansion box, 74Expansion Port (Compact), 191Expansion Port pinout (Compact/M128), 192EXT# change in BASIC 4, 204Extending the MOS, 84 External second processor, 17File buffers, ANFS, 148Filing System vector, 93Formatting characters, View, 162Formatting discs, 145Free run mode (keyboard), 39FSCV, 93General description, 12GSREAD format, 160Half-frames (TV) , 50Hardware Control Locations (B+), 168Hardware requirements, 1 MHz Bus, 70Hardware scroll, 43Hardware scroll and CRTC Multiplexer, 49HAZEL, 29HELP information (Master 128), 183High resolution screen modes, 42Host processor, 98I/O address space with ANFS, 157I/O processor, 99I/O processor, Z80 memory usage, 124INA/INC A (65C12 only), 244INC, 244INDirect Vectors, 95INSV 94Internal hardware strobes, 16Internal second processor, 16Interrupt flag register (User VIA), 58Interrupt handling, Z80, 122Interrupt request vectors, 96Introduction, 12INX, 245INY 246IRQ1V & IRQ2V, 96IRQs, 96 JMP,247Joystick/Mouse (Master Compact), 194JSR, 248Keyboard, 24, 33Keyboard buffer (Master Compact), 197 Controller, 37 matrix, 40 timings, 40KEYV 90Language processor, 12, 98LDA, 249LDX, 250LDY 251Library (ANFS), 157Light pens, 48LIST IF, 203LISTO, 203Logical colour, 20LSR, 252Luminance balance (TV), 21LYNNE, 28Machine Operating System. 77Master 128 Cartridge interface, 210Master 128 PCB links, 205Master 128 Sideways ROMs, 175Master 128 versus Compact, 190Master 128 versus Model B/B+, 171Master 128 VDU Commands, 176Master Compact Expansion Port, 191Master Compact PCB links, 208Master Compact test points, 207Master Compact versus Master 128, 190Matrix, keyboard, 33, 40Memory access control (80186), 143Memory consistency check, View, 164Memory format, View, 163Memory map, 27Memory map changes (Master 128), 186Misc functions control register, 45Model B/B+ versus Master 128, 171Modulator, 20MOS, 77MOS CLI buffer, 83MOS Function vector table, 86MOS version, read/display (B/B+), 165MOS version (Electron, B+) , 166MOS workspace, 83Monitor (280) , 122 138Monitor commands (80186),Motor control example, 59Multiplexer, CRTC, 48 17NEC mPD7002 A-to-D converter,NETV, 95Network collisions, 23Network number, 158NFS and ANFS, differences, 200NFS, ANFS, routines to check which, 159NMI Workspace, claiming, 118Non-Maskable Interrupts, 118NOP,253NTSC video output, 44Number register locations, View 164Optional component fitting, 209ORA, 254OS calls, Z80 (general), 120OS commands, new in Master 128, 172OSARGS (80186), 133OSARGS (ANFS), 154OSARGS (Tube), 109OSASCI (80186), 133OSBGET (80186), 132OSBGET (Tube), 109OSBPUT (80186), 132OSBPUT (Tube), 108OSBYTE (80186), 13c are required to selecta given ROM, although the power dissipation will be increased if all the ROMsin one column are inserted. A chip select will be driven low if an access toone of the segments (4 to 8) is required. If a cartridge ROM is required, thenthe Cartridge ROM chip select will be driven high. All chip selects are adecode of the CPU address most significant nibble. An output enable is turnedactive low during the CPU d2 period depending on which segment is required.The segment to be selected is determined by the binary number held within theleast significant nibble of ROMSEL.Overlaid RAM in ROM areaWhen the bit RAM is set in ROMSEL, accesses to the region &8000 to &8FFF areredirected from the currently selected ROM to a region of RAM referred to asANDY. It is the responsibility of the code which set RAM to clear it afteraccessing ANDY. This is necessary to ensure correct operation of software inROM.A further 64 Kbyte of RAM is available as four pages of 16 Kbyte from &8000 to&BFFF. The ROM slots 4,5,6 and 7 are not active when this RAM is link-selectedto be active.PAGE: 31Drawing not reproducedDRAM timingRAS is generated from 4M and 8M by the D-type IC28 pin 9. CAS for the mainDRAMs is generated from 2M, inverted by a NAND in IC34 to give phi2 IN, gatedwith DRAMEN which enables the main RAM, and finally gated with 4M throughanother NAND in IC34.PAGE: 324 SLOW DATA BUSSeveral internal components need to work with access cycles slower than theCPU's normal 1 or 2 MHz rates. These are: 1 ) Keyboard 2) Sound Generator 3) Real Time Clock/RAMDirect access of these devices is not recommended, as their operation may besubtly related to other functions, or be time-critical, or could causemalfunction if not performed correctly. The same functions may be provided bycompletely different hardware in earlier or subsequent products. For those whoneed direct access, rather than using the MOS, it is advisable to disable.interrupts whilst accessing any of these devices because the MOS may changesome of the settings whilst servicing an interrupt from another source.Memory LocationsAll these devices are accessed through the System VIA located at &FE40-9. TheSlow Data Bus is connected to the 8-bit A port at &FE41. This is referred toas PA[0:7]. The B port at &FE40 is the control bus.Slow Data Control Port (&FE40)Writing the following values will have the indicated effect:PA[7] DXXX XXXX - RTC/RAM Address strobe : Active highPA[6] XDXX XXXX - RTC/RAM Chip select : Active lowPA[7] XXXX D111 - Shift lock : Active lowPA[7] XXXX D110 -Capslock: : Active lowPA[0:3] XXXX D101 - Hardware Scroll 1 (HSI)PA[0:3] XXXX D100 - Hardware Scroll 0 (HS0)PA[0:3] XXXX D011 - Keyboard Enable (KBEN)PA[0:3] XXXX D010 - RTC/RAM Data Strobe : Active highPA[0:3] XXXX D001 - RTC/RAM Read Write : High for ReadPA[0:3] XXXX D000 - Sound Generator write : Active lowD is set high or low as needed.The hardware scroll bits HS[0:1] are used in VDU control.PAGE: 33KeyboardThe keyboard is accessed as a matrix of 8 rows by 13 columns. To access anyparticular key, it is necessary to assert KBEN and set the column and rowaddresses of that key on port A thus:PA[3:0] (outputs) are the column addressPA[6:4] (outputs) are the row addressPA[7] (input) is the key output - active low if pressed.An interrupt will be caused by CA2 via R13[0] (bit 0 of &FE4D) whenever a keyis pressed.Sound GeneratorWithin the MASTER 128, the sound generator chip is write-only. The write strobemust be asserted low for the data PA[0:7] to be written into it. Data must bestable during the 8ms in which the write strobe must be low.Real-time clock/CMOS RAMFifty bytes of battery-backed CMOS RAM are available within the real-time clockchip. Twenty bytes are used to store the system configuration, ten arereserved for future use by Acorn, ten are reserved for used by third-partymanufacturers and ten are available for used by the user. Extreme care shouldbe taken in the4OSBYTE (Tube), 107OSBYTE 0 (B+), 16514 (&0E), 9696 (&60), 160112 (&70), SO113 (&71), 50114 (&72) (B+), 166117 (&75), 50117 (&75) (B+), 166129 (&81) (B+), 166132 (&84) (B+), 166133 (&85) (B+), 166135 (&87) (B+), 167150 (&96), 52151 (&97), 52190 (&BE) (Master Compact) , 195239 (&EF) (B+), 167OSBYTE call summary, Master 128, 174OSCLI (Tube) , 106OSFILE (80186), 133OSFILE (ANFS), 154OSFILE (Tube), 109OSFIND (80186), 132OSFIND (Tube), 109OSGBPB (80186), 132OSGBPB (Tube), 110OSNEWL (80186), 133OSRDCH (80186), 133OSRDCH (Tube), 106OSRDSC (B+), 167OSWORD 5 and 6 (B+), 168OSWORD 114 (&72) bug, 193OSWORD 250 (&FA) (80186), 142OSWORD 255 (&FF) (Z80), 123OSWORD (80186), 134OSWORD (Tube), 107OSWRCH (80186), 134OSWRCH (Tube), 106OSWRSC (B+), 167Overlaid RAM in ROM area, 30Page signals, 73Paged Mode algorithm, 185Paging memory, 27 Page 0,77Page 0 and 1 (changes from B/B+ shown), 186 Pages 1 to &D, 78Page 2 to 9 (changes from B, B+ shown), 187Pages &A to &D (changes from B, B+), 188Pages &E to &7F, 80Pages &80 to &BF, 80Pages &C0 to &DF, 82Page &FC, 72, 73, 82Page &FD, 74, 82Page &FF, 82PAL video output , 44Palette, 20Palette control register, 46Parallel printer port, 52Parasite processor, 98Parasite protocols, 105PCB link settings, 189PCB links, Master 128, 205PCB links, Master Compact, 208PCB selection and test points, 205Pens,48Peripheral Bus, 63Peripheral Bus controller, 63Peripheral Bus, I/O definition, 64Peripheral Bus, timing spec, 65Peripheral control register (User VIA), 57PHA, 255PHP,256PHX (65C12 only), 257PHY (65C12 only), 258Physical colour, 20PLA,259PLP,260PLX (65C12 only), 261PLY (65C12 only), 262Pre-compensation (Master Compact), 193Print vector (user) , 92Printer port, parallel, 52Printing (ANFS), 154Private RAM, 188Processor, serial, 61RAM, 28RAM overlaid in ROM area, 30Random Access memory, 28Retries with ANFS, 158Read MOS version (Electron/B+), 166Read/display MOS version (B/B+), 165Real Time Alarm, 34Real time clock, 14Recursion in FOR loops, 204Refresh control, 49Registers, CRTC chip, 48REMV,94Reserved characters, View, 162RGB output, 44ROL, 263ROM Cartridge selection, 30ROMSELect, 30ROR, 264Row detection mode (keyboard) , 39RS423 buffering, 61RTCRAM access restrictions, 35RTI, 265RTS, 266SAA5050 devices, 43SAA5050 teletext character generator, 20SBC,267Schottky TTL loads, 72Screen display, 42Screen modes, 42Screen modes, teletext, 43Second Processor (Z80), 120Second Processor (80186), 131Second Processor architecture , 98Second Processor, external, 17SEC, 268SED,269SEI, 270Serial interfaces, 21Serial Processor, 61SERPROC, 61Shadow mode OSBYTE calls (B+), 166Shadow screen (B+) , 165Shadow screen memory, 82Shift register (User VIA), 54Sideways ROM headers, illegal, 185Sideways ROMs, new service calls, 175Sideways ROM (B+) , 169Signal definitions, 1 MHz Bus, 70Slow Data Bus, 32SN7694A sound generator, 14Soft Key definitions, 186Soft Key expansion buffer, 82Sound Generator, 14, 33STA, 271STX, 272STY,273STZ (65C12 only) , 274System configuration, 33System VIA, 15TAX, 275TAY 276Teletext adapter 72Teletext character generator, 20Teletext modes, 43Terminal Emulator, 160Terminal file transfer, 160Test points, Master Compact, 207Time & Date (ANFS), 157Time-dependent functions, 96Time-independent functions, 84Timing requirements, peripherals, 75Timings, keyboard, 40Track format, ADFS, 146Track format, DFS, 145TRB (65C12 only), 277TSB (65C12 only), 278TSX, 279TUBE, 16, 63, 69, 99Tube code in 1770 DFS ROM, 169Tube protocols (general), 101Tube, checking for presence, 114claiming, 114data transfer, 116filing system usage, 103hardware dependency, 106host protocols, 113initiating data transfer, 115Interrupt-driven operations, 110non-interrupt protocols, 106OS usage, 102OSARGS protocol, 109OSBGET protocol, 109OSBPUT protocol, 108OSBYTE protocol, 107OSCLI protocol, 106OSFILE protocol, 109OSFIND protocol, 109OSGBPB protocol, 110OSRDCH protocol, 106OSW direct control of this device to ensure integrity of thecomputer's configuration status. The MOS should be used for the normalreading/writing of the RAM. FX calls 162 and 163 (OSBYTES &A2,&A3) are used toaccess the RAM. OSWORDs &14 and &15 should be used to read/write the time.CMOS RAM AllocationAddress (offset) Function0 Station Number1 File server station number2 File server bridge number3 Printer server station number4 Printer server bridge number5 Default filing system/language6-7 ROM frugal bits (set/cleared by *INSERT/*UNPLUG)8 EDIT start-up settings9 reserved for telecommunications applications10 VDU Mode and *TV settingsPAGE: 3411 ADFS start-up options and floppy drive parameters12 Keyboard auto-repeat delay13 Keyboard auto-repeat rate14 Printer ignore character15 Default printer type, serial baud rate, ignore status and TUBE select16 Default serial data format, auto boot option, internal/external TUBE use, BELL amplitude17 ANFS configuration control (on hard reset) bit 0 : Claim two static pages at &0E00 bit 1 : Findlib bootstrap option bit 2 : Reserved bit 3 : User/Application bit 4 : User/Application bit 5 : Reserved for ANFS protection mechanisms bit 6 : Display version messages18-1920-29 Reserved for future use by Acorn30-45 For ROMs 0-15 (one per ROM)46-49 Available for user applicationsNote that the station number cannot be written to, and has to be accessed bycode similar to that listed in the RTC alarm section.Real Time Alarm FunctionsThe MOS does not provide control of the device's alarm facilities as these areonly available on a daily basis, i.e. the alarm cannot be programmed tooperate on a specific date. The alarm operates by generating an interrupt whenthe real time counters are equal to the alarm time registers.The connection of the clock chip to the system interrupt line is via ashorting bar on Link4. This would have to be fitted by the user. For the userwilling to reserve some of the other battery-backed RAM for the target date,the following routine should be used to access the alarm and control registers.It is similar to those within the MOS and obeys the rules for reliableoperation. It is in the style of BBC BASIC assembler.pbq=&FE40 :REM Port Bpaq&FE41 :REM Port Addraq=&FE43 :REM Port B data direction register : REM 1 = Output : REM 0 = InputPAGE: 35EQUB &02 :EQUB pbq DS activeEQUB &82:EQUB pbq Address strobe inactiveEQUB &FF:EQUB ddraq OutputsEQUB &0E :EQUB paq slow bus address (see note 1)EQUB &C2:EQUB pbq chip select activeEQUB &42:EQUB pbq Latch addressEQUB &41:EQUB pbq Select write modeEQUB &FF:EQUB ddraq OutputsEQUB &4A: EQUB pbq Data strobe activeEQUB &00:EQUB paq Write the data (see note 2)EQUB &42:EQUB pbq Data strobe inactiveEQUB &02:EQUB pbq Chip select inactiveEQUB &00:EQUB ddraq Inputs again Note 1 This address should be made variable as it will be necessary to access one of a number of registers. Note 2 Separate sequences may be necessary for read and write operations, depending on personal preferences.RTC RAM Access RestrictionsThe real-time clock section of the chip is updated from the real-time countersonce every second. It is important that the user program does not try to accessthem at the same time as this will give erroneous results. There are threeways that the chip gives notice that it is in the process of updating theregisters. These are documented in the manufacturers data sheet. Wherepossible it is recommended that an alternative approach be used which ensuresuser access. This is to set the SET (bit 7) flag in Register &B (the controlregister). It prevents the chip from updating the registers but does not affectthe counted time. When the SET bit is reset, the registers will be reset to thecurrent time approximately within the next second. Avoidance of this criticalrORD protocol, 107OSWRCH protocol, 106parasite protocols, 105register addresses, 113register locations, 116releasing, 116startup protocol 113transferring data, 116vectors. 1 05Tube/Filing System interlace, 117TV modulator 20TXA, 280TXS, 281TYA, 282UPTV 91URD (ANFS), 156Use of EPROMS for memory, 81User bytes in CMOS RAM, 33User library (ANFS), 157User Port, 52User print vector, 92User Root Directory (ANFS), 156User VIA aux control register 56User VIA data register 53User VIA interrupt flag register, 58User VIA peripheral control register, 57User VIA shift register, 54USERV, 90VDU Commands Master 128, 176VDU driver, 49VDU trailing zeros, 204VDU workspace allocations, 84VDU workspace, 83VDU18, 176VDU22, 176VDU23, 177VDU24 ,180VDU25, 180VDU26-255, 182VDUV, 91Vector table, 86Vectors in co-processors, 85Vectors in Sideways ROM/RAM, 85VIA, 15Video control registers, 45Video outputs, 44Video processor, 44View, 162View, formatting characters, 162View, memory consistency check, 164View , memory format, 163View, number register locations, 164View, reserved characters, 162Viewsheet, 164WD1770 FDC, 23WD1770 floppy disc controller, 146Wrong versions (ANFS), 158Z80 Escape processing , 122Z80 faults and events, 121Z80 I/O memory usage, 124Z80 interrupt handling, 122Z80 Monitor, 122Z80 OS calls (general), 120Z80 OSWORD call, 123Z80 Second Processor, 120*CDIR (ANFS), 149*command abbreviation clashes, 185*COMPACT (Master Compact), 193*CONFIGURE (Master Compact), 194*CONFIGURE commands (ANFS), 152*CONFIGURE FDRIVE (Master Compact), 194*CONFIGURE, 171*D (80186), 139*DIR (Master 128), 186*DOS (80186) , 139*DRIVE (Compact), 192*DRIVE (Master 128), 185*F (80186), 139*FLIP (ANFS), 149*FORMAT (Master Compact), 193*FS (ANFS), 150*FX0 (B+), 165*FX16 default (Master Compact), 197*FX25 (Master Compact), 198*FX112, 50*FX113, 50*FX114 (B+), 166*FX138 (Master Compact), 197*FX221-8 (Master Compact), 197*GO (80186), 140*HELP (ANFS), 149*I AM (ANFS), 150*LCAT (ANFS), 150*LEX (ANFS), 150*MON (80186), 140*OPT extra commands (ANFS), 153*PASS (ANFS), 150*POLLPS (ANFS), 151*PROT (ANFS), 151*PS (ANFS), 152*RENAME wildcards (Master Compact), 193*S (80186), 140*SR (80186), 141*STATUS commands (ANFS), 153*TFER(80186), 142*UNPROT (ANFS), 152*WDUMP (ANFS), 152*WIPE (ANFS), 151146818 RTC chip, 151770 Floppy Disc Controller (B+), 1691MHz Bus, 701 MHz Bus peripherals (note), 691 MHz External I/O , 171MHz Internal I/O , 152MHz Internal I/O , 164464 Dynamic RAM, 196502 Instruction Set, 2166522 VIA, 15 , 2165C12 (65SC12), 1965C12 & 65C102 opcode compatibility, 10665C12 Instruction Set, 2166845 CRT controller, 17 , 426850 ACIA, 216850 Control register settings, 626850 UART 616854 ADLC, 2280186 Co-processor 131 14480186 data buffer example,80186 error handling, 13580186 error messages, 13680186 Escape processing, 13880186 extra OSWORD call (0FAh), 14280186 Monitor commands, 13880186 OS calls, 131OSARGS, 133OSASCI, 133OSBGET, 132OSBPUT, 132OSBYTE, 134OSCLI, 134OSFILE, 133OSFIND, 132OSGBPB, 132OSNEWL, 133OSRDCH, 133OSWORD,134OSWRCH, 13480186 Second Processor,13180186 software interrupts, 1318271 code compatibility, 1691 MHz External I/O , 171MHz Internal I/O , 152MHz InteÉЊJ J/J®ã Žã `­É Ð­É ðñ­ ­ © © `­ ­ `(L,ã öä ŠH˜H $ h¨hª­ä (`­ä pSÉ æª®å ÐL Lä ÉðÉ ðÉðÉð!L ©…ª©L © îÿ¥ª)Ðõ`©€Må å `­ã ) ð©@Ðî©Àã `¢€Žã H)ߢ@ÉBð>¢ ÉIð8¢ÉSð2¢ÉWð,ÉQð(ÉXð$¢ÉY𢠿 ¢ ¿ h  ¢ ¿ ¢€©  ŠL h) …¨É娅¨Š%¨…¨ŠIÿ-å E¨å `æ ¢æ  © ñÿ­å ) ðP­é è ­ê é ­ë ê ­í ë ­æ Éf ­ì ê L ©ì í î ­å )ð¢½æ é ÊÐ÷©ç è é ­å ) ðNç Nç Nè Nè Né Nê Në ,å P¢½æ æ æ ÊÐó,å ©ÿî ­å )ð2¢½æ ï   >æ (>æ ˆÐôÊÐé º ¢½ï  J~æ (~æ ˆÐôÊÐì©  ©ÿ  ¢½æ  èà Ðõ©ÿL ©À©Lãv1.05$):f$=""‚”õ:çcat%:Û:ñ">> Scroll Version "ver$" - (C) J.G.Harston Buffer size: &";~max%;" (";max%;" bytes) <<"':ÿ".":ñ'"Press SHIFT-Escape to exit.":*FX4ŒDõ:cat%=£:f$=A$:çf$+ch$="":è†"File: "f$:çÀf$,1)="*":òdegion, or the overriding of it, must be done whenever the real time or alarmregisters are written.The code should be assembled to operate in sideways RAM (i.e. in the region&8000 to &BFFF). The program is essentially in two parts:a) To set the alarm time, an OSCLI command which will not conflict with anyother in the machine, e.g. *SETALARM hh:mm:ss should be devised. This involvesrecognising Service Call &04 (Offer Command). The program should interpretthe given time string as appropriate and load it into the alarm registers thenre- enable the counter-register transfers and finally enable the alarminterrupt by setting the AI E (bit 5) flag in Register &B.PAGE: 36b) To respond to the alarm, the code should respond to Service Call &05(Unknown Interrupt). The alarm flag - AF (bit 5) in Register &C should beexamined to ascertain whether the alarm has occurred or not. If so, theappropriate action should be taken and the call should be claimed, otherwisethe call should not be claimed. The interrupt will be cleared by readingregister &C.PAGE: 37 5 KEYBOARD CONTROLLERKeyboard OperationDuring free run mode, the keyboard column lines are continually scanned byincrementing a counter, decoding its outputs and pulling low a column line.Any key depressed will cause the interrupt to be generated. A signal, KeyBoardENable is generated to stop free running mode. The counter contents are thenloaded by CPU operation to determine on which row the key was pressed. The rowsare then individually selected to determine which key was pressed. KBDENC issupplied with data from the slow data bus:-PA0 to PA6 (slow bus connections):- PA0 to PA3 are the column select inputsand PA4 to PA6 are the row select inputs. PA7 is a three-state connectionwhich is driven active low when a row/column combination describes a depressedkey.PA7 (row data bit output):- This 3-state output provides the ROW data signal tothe host system. It is enabled by the nKBEN signal and its output is high ifthe row address set up on PA4-PA6 points to a row which is at logic low.R0 to R7:- The keyboard row input connections are normally held high byinternal pull-up resistors. If a key is depressed it will cause theappropriate row connection to be pulled low when its column is selected.C0 to C14:- These open collector column driving outputs are sequentially takenactive low in auto scan mode at a rate of 1 MHz. In polled mode (nKBEN activelow), the slow bus inputs PA0 to PA3 determine which output will be low. Theselected column output is a direct decode of these inputs.CA2:- Connected to the system VIA, this output will cause the VIA to generatean n IRQ. The line will be active low when an active key is detected.nKBEN:- Generated by the system VIA, this line is taken active low to enablethe row and column addresses to be determined by the Operating System.MHz1:- Timing reference for the positive edge triggered counter and the resetgenerator circuit.SWTI (switch input):- A transition from 5v to 0v or 0v to 5v on this inputwill cause an active low pulse of 200ms to be generated on pin22 (RSTO).PAGE: 38RSTO (reset output):- This open-drain output is triggered by a transition onthe Switch Input pin SWTI and provides a logic low output pulse of at least200mS. For example if SWTI is taken from 0v to 5v via a mechanical switch, theoutput will immediately fall to 0v, hold low for 200mS after switch bounce andthen rise to 5V again.VCCI VCC2 (positive supply):- These pins must both be connected to the positivepole of a suitable power supply.GNDl, GND2 (ground):- These pins must both be connected to the power supplyGND or RETURN line.1 R0 VCCI 402 R6 MHZl 393 R7 NKBEN 384 R2 PA4 375 R1 PA5 366 C11 PA6 357 C10 PAO 348 C12 PAl 339 C0 PA2 3210 GND2 PA3 3111 C2 VCC2 3012 C9 PA7 2913 C4 CA2 2814 C5 R5 2715 C6 R4 2616 C8 R3 2517 C7 C13 2418 C3 C14 2319 C1 RST0 2220 GND1 SWT1 21KBDENC connectionsThe keyboard enco ô > Scroll!ô Scrolling text file displayòxtr:ver$="1.10":c$="128"((ë&83:h%=24:w%=79:ç“>&4000:ë&80:h%=312Aòinit:A$=¤OS_GetEnv:lp$=¤cl("-l"):tt$=¤cl("-4"):ch$=¤cl("-c")<6quit$=¤cl(" -q"):Z$=¤cl("-?"):A$=¤cl(" "):òasm:ògoFvç§" "+A$+Z$," -?"):ñ"Syntax: Scroll (-lp ) (-4 ) |-chan + (-quit )":òend(£):àPçA$="""""":A$=""ZCcat%=A$+ch$="":çmax%<2500:ñ"Not enough memory to run":òend(£):àdçlp$="":lp$=¤FindLPnî… ç¤err „ A$<>"":òend(£):àxEX%=ctrl%:Y%=X%256:çpr% €f$<>"":pr%=£:ògo:òcon:cat%=¤lp(f$):f$=""‚”õ:çcat%:Û:ñ">> Scroll Version "ver$" - (C) J.G.Harston Buffer size: &";~max%;" (";max%;" bytes) <<"':ÿ".":ñ'"Press SHIFT-Escape to exit.":*FX4ŒDõ:cat%=£:f$=A$:çf$+ch$="":è†"File: "f$:çÀf$,1)="*":òdis:ÿf$:òcon–'ýÀf$,1)<>"*":cat%=¤lp:f$="":ýA$<>"" òend(£):àª:´Ýòend(F%):òcl:*FX4¾ *FX229È *FX225,1Òòdis:çF%:áÜ&çquit$<>"":ï13:ñ"Exit";:òos(quit$)æáð<ݤerr:çŸ<>17:ö:çŸ<128 € Ÿ<>17:ñ" at line ";ž; ‹ çŸ<>17:ñúcat%=Ÿ=17:òcl:=¦-1#Ýòinit:cat%=¹:ch%=0:pr%=£:f$=""@Max%=“-’-900:Þctrl%20,data% Max%+4:end%=data%+Max%:max%=Max%X%=ctrl%:Y%=X%256:á",ݤcl(l$):ê I%:ç—l$=32 € A$<>"":A$=" "+A$,SI%=§A$,l$):l$="":çI%:l$=ÁA$,§A$," ",I%+1)+1):çÁA$,I%,1)<>" ":l$=Àl$,§l$," ")-1)6?çI%:çÁA$,I%,1)=" ":A$=ÀA$,I%-1) ‹ çI%:A$=ÁA$,§A$,l$)+1+©l$)@=l$JÝòcl:çch%:A%=ch%:ch%=0:Ù#A%Tá^Ýòos(c$):çÀc$,1)="*":ÿc$:áh:I%=§c$," "):çI%:ÿ"KEY0 |@"+Ác$,I%+1)+"|M":*FX138,0,192r ×c$:á|ݤlp:len%=0:çf$+ch$="":=£†@çch$<>"":len%=§ch$,"+"):ch%=»Àch$,len%-1):len%= Ách$,len%+1)8çch$="":ch%=Ž(f$):çch%=0:ñ"File '"f$"' not found":=£šslen%=(¢#ch% €(len%=0))+len%:pt0%=#ch%:çlen%end% €ch%:òdnê€çi%=8 €ptr%end% €ch%:òdn?çI%=2 €ptr%çI%=4 €ch% €fst%0:fst%=0:ògbpb(max%,0)XçI%=5:top%=data%:òpg:ý0b'ç(I%€&FE)=6:c$=Ã(»c$‚32):òon:òpg:ý0lç(I%€&FE)=16:òprv5çI%=18 €tt$<>"":òend(¹):ñ"Mode7";:òos(tt$+" "+f$)€ýI%=1:*FX229Š *FX225,1”=¹ž:¨xÝòpg:Û:ï13:ptr%=top%:õòp(ptr%):ptr%=ptr%+1+©$ptr%:ý¼>=h% „ptr%>=data%+len% „ptr%>=end%:ç¼=top%:çdata%+1+©$data%=top%:t%=data%Ú=top%=t%:t%=ptr%-100:õt%=t%+1+©$t%:ýt%+1+©$t%=ptr%:ptr%=t%ä?ï30,11,13:òp(top%):ñŠ0,h%);:òln:çptr%+1+©$ptr%data%+len%-fst%:ptr%=t%:áøÝòdn:çfst%+max%>=len%:á-f%=fst%+max%2:çf%+max%>len%:f%=len%-max% off%=f%-fst%:çoff%=0:áend% „A%>data%+len%:á¢pÝòpr:ñ‰(79);½13;"Print out ";f$;" Printout with *";:çlp$<>"":ãi%=1¸ ©lp$+1:ÿ"FX138,0,"+×Álp$+" ",i%):í¬Cè""lp$:çlp$="":ï7:ñ"No printout command found";:A%=¦(200):òpder scans the keyboard matrix, interrupting the CPU when a keyis pressed. The MOS then puts the device in manual mode and scans the columnsuntil it finds one where a key has been pressed. It then scans the rows untilit finds one where a key has been pressed. It then goes on to check othercolumns and rows to find out if any other keys have been pressed. Thiscontinues at 10ms intervals (under the control of the system timer) until nokeys are pressed, at which point the MOS switches the device back to automaticscanning. The operation of this circuit can be split into three modes.PAGE: 39Mode 1 - Free runThis is the state assumed during normal operating periods with no key pressed.The keyboard is constantly scanned, with no intervention from the CPU, until akey is pressed. A four-bit counter, clocked by a 1 MHz signal drives afour-to-fifteen line decoder. This causes a logic low to ripple through C0 toC14. Should any key be pressed, the column in question will be connected tothe relevant row, which will pull one of the inputs to the 7NAND gate low. Asthe other six inputs are all pulled high, the NAND output will go high andthus generate an interrupt signal on pin CA2.Mode 2 - Column detectionThe interrupt signal is registered in the host system which then takes acloser look at the keyboard. The Operating System keyboard scan routine isentered and individual addresses may be set up on PA0 to PA3. These aresynchronously loaded into the counter while nKBEN is low, thus causing eachkeyboard column to be individually scanned. The interrupt CA2 may be examined after each counterload to see if the correct column has been reached. If this is so then thecolumn address is held on the counter and stored for future reference, if notthen the next address is loaded into the counter.Mode 3 - Row detectionHaving discovered and held the column address, the host may now set upaddresses on PA4 to PA6. These are fed to an eight-way data selector and causeone of the eight rows to become available on the W output in an inverted state. Should the correct row be found, W will go high and the current address willbe stored.PAGE: 40Keyboard MatrixThe keys are physically arranged as a QWERTY type keyboard with ten functionkeys, four cursor control keys and a nineteen-key numeric keypad. C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12R0 ESC f1 f2 f3 f5 f6 f8 f9 A @ 4 5 2R1 TAB Z sp V B M , <. >/ ?cpy 0 1 3R2 SHIFT LOCK S C G H N L +; (] del # * ,R3 CAPS LOCK A X F Y J K @ *: ret / del .R4 1! "2 D R &6 U O P )[ @ + retR5 f0 W E T 7' I )9 0 / @ 8 9 R6 Q #3 $4 %5 `4 (8 `7 =- @ 6 7 R7 SHIFT CTL INKEY NUMBERSkey Inkey Number key Inkey Numberf0 -33 4 -19f1 -114 5 -20f2 -115 6 -53f3 -116 7 -37f4 -21 8 -22f5 -117 9 -39f6 -118 , -103f7 -32 _ -24f8 -119 . -104f9 -120 / -105PAGE: 41key INKEY number key INKEY numberA -66 [ -57B -101 \ -121C -83 ] -89D -51 ^ -25E -35 - -41F -68 : -73G -84 ; -88H -85 @ -72J -70 ESCAPE -113K -71 TAB -97L -87 CAPS LOCK -65M -102 SHIFT LOCK -81N -86 CTRL -2O -55 SHIFT -1P -56 SPACE -99Q -17 DELETE -90R -52 RETURN -74S -82 COPY -106T -36 ­ -58U -54 ® -26V -100 -122W -34 ¯ -42X -67 keypad 0 -107Y -69 keypad 1 -108Z -98 keypad 2 -1250 -40 keypad 3 -1091 -49 keypad 4 -1232 -50 keypad 5 -1243 -18 keypad 6 -27keypad / -75 keypad 7 -28keypad £ -91 keypad 8 -43keypad * -92 keypad 9 -44keypad, -93 keypad + -59keypad RETURN -61 keypad - -60keypad DELETE -76PAGE: 426 SCREEN DISPLAYScreen OutputThree chips are primarily responsible for providing the screen output:-a) Acorn VIDPROC ULA chipb) 6845 cathodg:á¶>pr%=¹:òdis:ñ"Printing...";:ÿlp$+" "+f$:ògo:òon:pr%=£:òpg:áÀ:ÊݤFindLP:ç¤i("lp")=1:="lp"ÔA%=¤i("%.lp"):çA%=1:="%.lp"Þ!çA%=2:ç¤i("%.lp.#"):="%.lp.#"è!çA%=2:ç¤i("%.lp.*"):="%.lp.*"òç¤i("$.lp"):="$.lp"üç¤i(":0.$.lp"):=":0.$.lp"=""6ݤi(f$):êA%:$data%=f$:A%=5:!X%=data%:=(º&FFDD)€&FF:$:ݤOS_GetEnv:êA$,A%,X%,Y%:X%=1:os%=((º&FFF4)€&FF00)256.Hç¦(0)=0:õ A%=¦(0):A$=A$+½A%:ý A%=-1:ÿ"KEY0":=ÀA$,©A$-1+(ÂA$,2)<" "))8Pços%=6 € >&8000:È™ "OS_GetEnv" ¸ A$:=ÁA$,1+§A$," ",1+§A$," ",1 +§A$," "))))BvX%=ctrl%:Y%=X%256:A%=9:?X%=0:X%!1=data%:!data%=0:Ö&FFD1:ç!data%€?data%+data%?2<>8:data%?(1+?data%)=13:=$(data%+1)L=""V:`Ýòon:çm%:ÿ"CODE "+c$játÝòoff:çm%:ÿ"CODE 0"~áˆÝòcon:çm%:ÿ"CODE 251"’áœÝòdis:çm%:ÿ"CODE 253"¦á°Ýògo:çm%:ÿ"disp ON":Ạòc(-1):áÄÝòp(P%):çm%:ñ$P%:áÎ õòc(?P%):P%=P%+1:ýP%?-1=13:áØ=Ýòasm:m%=os%<>6:çm%:î…:î… ‡:ñ"Can't find *disp":òend(£):àâáì Ýòxtr:ôöòreloc(&500,3):ç(¦-256 €&F0)<>&A0:A%=:õA%=A%+1+©$A%:I%=§$A%,½&DD+½&F2+"xtr:"):ýI%:A%!(I%+5)=!(¸P-3+2*(?(¸P-3)=0)):Ò=A%+I%+8-2*(?(¸P-3)=0):á'á:ô Last line MUST end with ENDPROC !Ýòc(A%):çA%<0:flg%=0:out%=1:áçA%<32:òctrl(A%):áçflg%>127:òflg(A%):á(out%=out%+1:çA%=32:A%=92çflg%=0:ï A% ‹ òout(A%)<áFÝòctrl(A%)P%çA%=9:ãz%=(out%€ 7)¸ 7:òc(32):í:áZçA%=13 „ A%=10:ñ:out%=1:ád%çA%=28:flg%=flg%‚ 1:á:ô Underlinen5çA%=29:flg%=flg%„ 128:á:ô Wait for next characterxá‚.Ýòflg(A%):flg%=flg%€ 127:çA%<65 „ A%>126:áŒb%=0:a%=A%<96:A%=A% € &DF–çA%=—"B":b%=&FD çA%=—"H":b%=&BFªçA%=—"I":b%=&F7´çA%=—"Q":b%=&BB:ô Almost¾çA%=—"S":b%=&EFÈçA%=—"W":b%=&FBÒçA%=—"X":b%=&BBÜçA%=—"Y":b%=&DFæçb%=0:ñ"(";½A%;")";:áð'flg%=(flg%€ b%)„(a% € (b% ‚ 255)):áúÝòout(C%):çC%=9:C%=32 ê z%,a%:A%=10:?X%=C%:Ö &FFF1)ç(flg%€ 1):X%?8=255:ô or X%?8 EOR 2554ç(flg%€ 2):ã z%=1 ¸ 8:X%?z%=X%?z% „(X%?z% 2):í"Zç(flg%€ 8):X%?1=X%?1 4:X%?2=X%?2 4:X%?3=X%?3 2:X%?4=X%?4 2:X%?7=X%?7*2:X%?8=X%?8*2,>ç(flg%€ 48):X%?2=X%?3:X%?3=X%?5:X%?4=X%?6:X%?5=X%?7:X%!6=068ç(flg%€ 32):X%!8=X%!5:X%!4=X%!1:X%?1=0:X%?2=0:X%?3=0@*ô Sub/Super need a bit of modificationJ¶ç(flg%€ 4):ãz%=1 ¸ 8:?(X%+9+z%)=X%?z%:X%?z%=(X%?z% € 128)+(X%?z% € 128) 2+(X%?z% € 64) 2+(X%?z% € 64)4+(X%?z% € 32) 4+(X%?z% € 32) 8+(X%?z% € 16) 8+(X%?z% € 16) 16:í:òoutBT ç(flg%€ 4):ãz%=1 ¸ 8:X%?z%=?(X%+z%+9):X%?z%=(X%?z% € 1)+(X%?z% € 1)*2+(X%?z% € 2)*2+(X%?z% € 2)*4+(X%?z% € 4)*4+(X%?z% € 4)*8+(X%?z% € 8)*8+(X%?z% € 8)*16:í^ òoutB:áh ÝòoutBr‚ç(flg%€ 68)=68:ï 23,255:ãz%=5 ¸ 8:ï X%?z%,X%?z%:í:ï 10,255,8,11:ãz%=7 ¸ 0 ˆ -2:?(X%+z%+1)=?(X%+1+z%2):?(X%+z%)=?(X%+1+z%2):í|ƒç(flg%€ 68)=64:ï 23,255:ãz%=1 ¸ 4:ï X%?z%,X%?z%:í:ï 11,255,8,10:ãz%=0 ¸ 7 ˆ 2:?(X%+z%+1)=?(X%+5+z%2):?(X%+z%+2)=?(X%+5+z%2):í†'ï 23,255:ãz%=1 ¸ 8:ïX%?z%:í:ï 255:áGÝòreloc(S%,X%):A%=133:X%=X%„&80:A%=(º&FFF4 €&FFFF00)256:çA%-’>S%: B%=(+(A%-’-S%))€&FF00:ñ"Relocating to &";~B%:ãA%=0 ¸ ’-+4 ˆ4:A%!B%=A%!:í:A$="":õB$=¿(0):çB$<" " € B$<>"":B$="|"+½(64+—B$)¤:A$=A$+B$:ýB$="":ÿ"KEY0 RUN|M"+A$:ÿ"FX138,0,192":Ð=B%:à®áÿents of tCH."Scroll"llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllŸbü!À#Å%Ç*´4S°8W±:S±AR#R€CÆEÈJµTÔXW°ZÔa-°b-±ÿ© `˜H ð©| ôÿ© ôÿh¨ Í Î ð©…¨…©…ª…«¢¨© Úÿ ×  L@ © îÿ©LÎÿ Ý ­ É< Í ¢$ÿ0° ×ÿ°¼É É`ð%É£ð!è À LB ÉðÑÉ ðÍÉ ð@É ðÉð&ÉðÐÊ©@Ð Í L@ L ×ÿ°øé0´É_°° í LB ­ I ) ` í LB Š)ª© À èŠÉÐõLB ©ÐH© Ç hLîÿ å ­ ÉBöî © `, P å î ©LÀ Ž! i¢ÝÄðHè½ÄúhèÐî ¼ è½Ä) À ½Äò®! `¢¨  ðŒ Úÿ±¨ÉðN¢É+Т@ Æ ðAŽ ˜Hȱ¨É!°ù Ç ð §  Ç ð §  he¨ª©e©¨©@ Îÿ¨ð+© îÿ© í L ÜSyntax: lp (+) ()ÖNot found©…ª±¨É0)H¥ª eª …ªheªÈÐ楪`ȱ¨É ðùÉ`V1.13, 57PHA, 255PHP,256PHX (65C12 only), 257PHY (65C12 only), 258Physical colour, 20PLA,259PLP,260PLX (65C12 only), 261PLY (65C12 only), 262Pre-compensation (Master Compact), 193Print vector (user) , 92Printer port, parallel, e ray tube controllerc) Acorn CHROMA MSI video matrixing chipThe video processor takes a byte-wide data stream from memory, serialises itaccording to the screen mode in use, passes it through a palette to providelogical to physical colour transformation and on to the RGB outputs. From herethe video data is buffered for connection to an RGB monitor and mixed for usewith the composite video and colour television outputs.High Resolution ModesThe 6845 generates a linear memory address sequence which increments every0.5ms or 1 ms, depending on the video bandwidth selected and video data format.The amount of memory reserved for screen use is also varied. The availableoptions areVideo Data Formats'Mode' Format Reserved Memory Pixels/Byte Bytes 0 8 20K 1 4 20K 2 2 20K 3 8 16K 4 8 10K 5 4 10K 6 8 8K 7 Teletext 1K 128 8 20K ] 129 4 20K ] 130 2 20K ] Reserved 131 8 20K ] in 132 8 20K ] LYNNE 133 4 20K ] 134 8 20K ] 135 Teletext 20K ]PAGE: 43All modes except 7 and 135 display a bit-mapped image of the reserved memory.The 6845 may be re-programmed to display any arbitrary section of memory. Ifthis is done, however, the hardware scrolling will not work correctly, as itassumes that the screen memory is in its usual location. The screen alwaysends at &7FFF and starts 1,8,1 0 or 20K below, depending on the selected mode.The selection of video bandwidth and data format is performed by programmingthe VIDPROC. The cursor size and position is also controllable by VIDPROC.Special measures have been taken to ensure correct cursor operation in theTeletext modes.TeletextThe Teletext modes do not generate a bit mapped display, but a character cellone. The character/graphics ROM within a SAA5050 device generates RGB signalsaccording to the desired character/graphics information within the reservedmemory space. Each byte of memory is therefore just a definition of thecharacter/graphics symbol required.Other SAA505X devices may be used when different languages are required. Only1 Kbyte of memory is needed for either of the Teletext modes, although 20K isreserved for it in mode 135. The MOS uses the spare 19K to speed upinter-filing system file transfers but the user may use this memory if no suchtransfers are to be done. VIDPROC has to be re-programmed to use the SAA5050RGB outputs. The 6845 is still used to generate the cursor. As a delay of 2.75ms will occur between reading a character from RAM and outputting theappropriate RGB signals, the 6845 has to be programmed accordingly. The'start' of screen signal is given a 1 .5-byte time offset and the SAA5050 hasa further one-byte time offset to restore the correct cursor/data phase.VIDPROC has further adjustment which allows for the cursor to be adjusted topixe accuracy.Hardware ScrollScrolling may be achieved in any mode by re-programming the 6845 start ofscreen address to an integral number of video lines further down the memory mapthan the nominal start of screen. This causes the linear address generator toattempt to display an end of screen, which is out of the reserved video area.To overcome this effect, hardware scrolling is provided with a variable addresswrap-around. When the address generator would otherwise attempt to accessout-of-screen RAM, its addresses are modified to point to the gap between theoriginal start of screen and scrolled start of screen. When this is done, onlythe end of screen needs to be written over in RAM. (If this is not done, theentire screen appears to roll-over). The amount of modification to be used iscontrolled by two nodes; C0 and C1.PAGE: 44 ݤS="Join"ë128 Ó=&2000(:ñ'"File Joiner By C.J.Richardson For 8-Bit Software."'2*.<ñ'"Finished Filename: "Fè J$P F%=® J$Zñ'"Name of Files to Join: "dè J$n!ñ'"Number of files to join? "xè I%‚ B%=&900ŒC%=0–õ  C%=C%+1ªC$=J$+à (C%)´ G%=Ž C$¾9ç ¢#G%>&6000 ñC$;" Needs making smaller!":Ù#G%:Ù#F%:àÈòldÒÙ#G%Üòsvæ ý C%=I%ðÙ#F%úñ'"Done!"àÝòld H%=¢#G%"A%=4,X%=B% ƒ 2566Y%=B% 256@ B%?0=G%JB%!1=&2000T B%!5=H%^ Ö&FFD1hárô|Ýòsv†A%=2X%=B% ƒ 256šY%=B% 256¤ B%?0=F%®B%!1=&2000¸ B%!5=H% Ö&FFD1Ìáÿlllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll ݤS="Split"ë128 Ó=&2000(<ñ'"File Splitter By C.J.Richardson For 8-Bit Software."'2*.<ñ'"Filename to split:"Fè J$P F%=Ž J$Zñ'"Name of parts: "dè J$n B%=&900xC%=0‚õŒòld– C%=C%+1 C$=J$+à (C%)ª G%=® C$´òsv¾Ù#G%È ýÅ#F%ÒÙ#F%Ü3ñ'"Done!"'"Parts are named from ";J$;"1 To ";C$æàðÝòldú-ç ¢#F%-#F%>&4FFF H%=&5000 ‹ H%=¢#F%-#F%A%=4X%=B% ƒ 256Y%=B% 256" B%?0=F%,B%!1=&20006 B%!5=H%@ Ö&FFD1JT%=0Tç #F%=¢#F% á^ S%=&6FFFhD%=0rõ| D%=D%+1† S%=S%+1 T%=T%+1š R%=š#F%¤ ?S%=R%®ý?S%=13 „ ?S%=10 „ D%=80 ¸áÂÝòsvÌA%=2ÖX%=B% ƒ 256àY%=B% 256ê B%?0=G%ôB%!1=&2000þB%!5=H%+T% Ö&FFD1áÿllllllllllllllllllllllllllllllllllllllllllllllllllllllllllthin this text. the terms :-Tube and Econet are registered trade marks of Acorn Computers LimitedView and Viewsheet are registered trade marks of Acornsoft LimitedDOS Plus, Concurrent DOS and C/PM are the registered trademark of DigitalResearch Inc.All references in this book to the BBC Microcomputer refer to the computerproduced for the British Broadcasting Corporation by Acorn Computers Limited.This book was computer typeset by Ian Bishop Laggett,Ideal Software Consultants, 11 Hathaway Close Luton, Bedfordshire,AcknowledgementsThanks to David Beil, Roger Cullis, Dave Futcher Adrian Bishop Laggett and allthose people who made the publication of this manual possible.CONTENTS1. Master Series architecture 12Introduction 12core Machine 12Internal I/O 13External I/O 13 Internal Input/Output 14Slow peripherals 14Sound Generator 14Real time clock with RAM 14Configuration Status 15Clock 151MHz Internal I/O 15System VIA 152MHz Internal I/O 16 External Input/Output 171MHz External I/O 17Analogue Port 17Light Pen 172MHz External I/O 17External Second Processor 172. Circuit description 19Detailed Circuit Operation 243. Memory organisation 27Memory Map 27Random-Access Memory 28ROMSEL 30Overlaid RAM in ROM area 30DRAM timing 314. Slow data bus 32Memory Locations 32Slow Data Control Port 32Keyboard 33Sound Generator 33Real time clock/CMOS RAM 33CMOS RAM Allocation 33Real Time Alarm Functions 34RTCRAM Access Restrictions 355. Keyboard controller 37Keyboard Operation 37KBDENC connections 38Keyboard Matrix 40Timing diagrams 40Free running mode 40Column scan mode 41Row scan mode 416. Screen display 42Screen Output 42High Resolution Modes 42Teletext 43Hardware Scroll 43Video Output 44Video Processor 44Control Registers 45Miscellaneous Functions Control Register 45Palette Control Register 46Cathode Ray Tube Controller 46CRTC Multiplexer 48Internal Timing 49Hardware Scroll 49Refresh Control 49Multiplexing 49VDU driver 497. User Port 52Timers 52User Port Data Register 53User Port Data Direction Register 53Timer 1 Low Order Counter/Latch (R/W) 53Timer 1 High Order Counter (R/W) 5Video OutputThree outputs are provided for displaying video data. These are:a) PAL/NTSC encoded, UHF carrier. On channel 36 with 1.5mV into 75 ohm.b) Composite video. This is a 1v peak-to-peak signal.c) Digital Red-Green-Blue (RGB) - these are approximately 75 ohm outputs.For use with NTSC, the modulator has to be changed from UM1233/E36 to a VHFequivalent. Provision is made for selection of either one of two channels withVHF. A Molex type link has to be inserted for this.Flow chart not reproducedPAGE: 45Control RegistersThere are two control registers. The first contains miscellaneous controlfunctions, the other dictates the contents of the palette.Table not reproducedNotesbit 0 is re-programmed by the MOS at intervals to cause physical flashingcolour to alternate between its standard values and the (binary) logicalcomplement.bit 1 dictates whether the RGB signal supplied to the external buffers comesfrom the palette output or the Teletext character generator.bits 5-6 The cursor is 'on' for a number of byte-times, depending on the screenmode.PAGE: 46Palette Control Register (write only)bits 0-3 - physical colourbits 4-7 - logical colourThese are programmed together so that a certain physical colour is associatedwith a particular logical colour.In two colour modes, bit 7 dictates the colour- Eight locations must be programmed.In four colour modes, bits 7 and 5 dictate the colour- Four locations must be programmed for each logical colour.In eight colour modes, Bits 7 to 4 dictate the colour- One location must be programmed for each logical colourThe principle is that the remaining locations must be set to the same value asthe selected logical colour. If bits 7 and 5 in a four colour mode were 0, 1and physical colour 0,1,1,1 was to be written to this location, then 0,1,1,1must be written to all logical colour locations obtained with the fourcombinations of bits 6 and 4 while 7 and 5 are held as 0,1.The Cathode Ray Tube ControllerThe Cathode Ray Tube Controller (CRTC) is the heart of the microcomputer’svideo display circuitry. Its primary function is to display all video data inthe memory on a raster scan display device i.e. a television or a monitor.The CRTC chip used in the Master Series of microcomputers has sixteenregisters, which can all be accessed by the command VDU 23,0. Themanufacturer's data sheet gives the exact effect of the registers, and onlythe default values for each screen mode and the two control bits HS0 and HS1in the slow bus control latch are listed here. The bits HS0 and HS1 affect thescrolling function by extending the maximum address in the display memory map,as seen by the CRTC. Note all the numbers are in Hexadecimal.PAGE: 47CRTC chip registersTable not reproducedNotes1) These only apply if the screen position has not been modified by*CONFIGURE,Or a subsequent *TV command.2) These only apply if the interlace has been turned on by *CONFIGURE, or asubsequent *TV command.3) These values are only valid before hardware scrolling has been used.4) On reset, these registers are set to the screen start address, but theactual position will depend on how much screen output has been generated bylanguages, filing systems etc.PAGE: 485) Light pens can be connected either to the Analogue Port at the rear of themachine, or to either of the Cartridge Sockets just behind the keyboard. A low pulse on any of these connections to the light pen strobe will cause thecurrent scan position to be latched in the light pen position registers, R16and R17. The accuracy of the measurement will depend on the sensitivity of thelight pen. The figures given should be subtracted from the R16,R17 contents toyield the actual screen position, assuming ideal optical conditions. Theadjustment arises out of the different screen start addresses. The final X,yco-ordinates are:X = ((R16,17 - Offset) DIV (characters per line))/Light Pen Cell ModifierY = (R16,17 - Offset) MOD (characters per line)These offsets are only valid befor3Timer 1 - Low Order Latch (R/W) 54Timer 1 High Order Latch (R/W) 54T2 Low Order Counter/Latch (R/W) 54T2 High Order Counter (R/W) 54Shift Register 54Auxiliary Control Register (R/W) 56Peripheral Control Register 57Independent Mode 57Interrupt Flag Register 58Interrupt Enable Register 59Example of motor control 598. Serial Processor 61UART 61SERPROC 61Buffer Components 61Control Register Settings 629. Peripheral bus controller 63Internal Timing 63Buffer Control 63Timer 63I/O Definition 64AC Parametric Test Information Timing Specifications 65SA data latching point 66SL data latching point 66C Bus Drive Waveforms 67B Bus Drive Waveforms 68E bus drive waveforms 6910. 1MHz Bus 70Signal definitions 70Hardware requirements for 1MHz expansion bus peripherals 72Derivation of valid Page signals 73Address space allocation 73Page FC 73Page FD 74Timing requirements 7511. Machine Operating System 77Address space map 77Page 0 77Pages &1 to &D 78Pages &E to &7F 80Pages &80 to &BF 80Pages &C0 to &DF and page &FF 82Page &FC 82Page &FD 82The Second 32k of RAM. 82VDU Workspace 83VDU workspace allocations 84Extending the MOS 84Time-independent Functions 84Vectors in co-processors 85Vectors In Sideways ROM/RAM 85MOS Function Vector Table 86Entry pointed vectors 87Vectors without MOS entry points 87EVENTV 8BRK instruction 88BRK instruction in single processor systems 89BRK instruction in co-processor systems 90USERV 90KEYV 90VDUV 91UPTV 92FSCV 93INSV 94REMV 94CNPV 94NETV 95INDirect Vectors 95Time dependent functions 96EVENTV 9612. Dual processor systems 98Second processor architecture 98The Tube 99Tube Architecture 100Tube Protocols 101Operating System Usage 102Filing System Usage 103PARASITE Protocols 105Vectors 105Hardware Dependency 106Host Hardware 106Parasite Hardware 106Non-interrupt protocols 106OSWRCH 106OSRDCH 106OSCLI 106OSBYTE 107OSWORD 107OSBPUT 108OSBGET 109OSFIND 109OSARGS 109OSFILE 109OSGBPB 110Interrupt driven operations 110Start-up protocol 113Register Addresses 113Tube protocols 113Host Protocols 113Check for presence of the Tube 114Claiming the Tube 114Initiating data transfer 115Transferring data 116Releasing the Tube 116Register Locations 116Tube/filing system interface 117LOAD/SAVE addresses 117Use of the Non Maskable Interrupt 118Claiming NMI workspace 118Hardware access to the NMI 11913. Z80 Second processor 120Operating system calls 120Faults and events 1216502 Faults 121Z80 Faults 121Events 121Escape processing 122Interrupt handling 122NMI Nonmaskable interrupt 122INT Interrupt request 122Z80 Monitor 122Z80 OSWORD call 123I/O Processor Memory Usage 124Screen Control 125BBC Microcomputer Control Codes 125Terminal Emulator Control Codes 125GSX Functions 126Character I/O under CP/M 126Device assignments 126The IOBYTE facility 127Device characteristics 129The System Patch Area. 13014. 80186 coprocessor 131Operating System Calls 131OSFlND 132OSGBPB 132OSBPUT 132OSBGET 132OSARGS 133OSFILE 133OSRDCH 133OSASCI 133OSNEWL 133OSWRCH 134OSWORD 134OSBYTE 134OSCLI 134Error Handling by the 80186 Monitor 135Error Handling by stand-alone languages e hardware scrolling has been used. For thisreason it is often advisable to restrict light pen use to text or graphicsusing graphics mode. The Light Pen Cell Modifiers are necessary as the 6845 isclocked at different clock speeds in different modes, so in a given time, the6845 sees a different number of character cells from the one the viewer sees.The modifiers allow this to be taken into account.6) Each character cell is eight bytes deep as the 6845 imposes this format onthe memory map; so each entry in this line of the table is the number ofcharacter positions multiplied by eight. This figure can be used to establishthe start and end address of any scan row, given the screen's start address.7) The VIDeo PROCessor (VIDPROC) control register's least significant bit ischanged in all modes except Mode 7 to cause the colours to flash.CRTC MultiplexerThe CRTC Multiplexer converts the CRTC's eighteen-bit address into twoeight-bit addresses for the row and column parts of the DRAM's video cycle. Italso provides the hardware scroll logic to keep the addressed memory withinthe screen's 20Kbyte boundaries.PAGE: 49Internal TimingThe device uses a slightly delayed version of the DRAMs' nRAS strobe to selectbetween the row and column parts of the address.Hardware ScrollThe hardware scroll address modification as described in the section on 6845register values (MOS chapter) is performed by logic within this device. Someof the CRTC address lines are used in a non-standard way. The MA13 line isused as a 'Bit-Mapped or Teletext' mode indicator and is used to modify theaddress scan accordingly.Refresh ControlIn the bit-mapped modes, the memory is scanned often enough to render explicitrefresh unnecessary. In the Teletext modes, the addresses of non-displayedlocations (as accessed in the 24ms per line when the display is inactive) aremodified to produce sequential scanning and hence maintain the refresh.MultiplexingThe address is output, one half at a time for each of the Row and Columnaddresses. One of four eight bit fields may be selected:1) Bit mapped display - low order address2) Bit mapped display - high order address3) Teletext display - low order address4) Teletext display - high order addressThe VDU driverThe VDU Driver is extensively covered in Part 1 of the Reference Manual.However, by programming in machine code, the hardware may be accesseddirectly to give additional display modes, such as a 640*512 MODE. This is atwo-colour mode which uses both the main and shadow screen memories to storealternate half-frames of an interlaced synchronisation and video picture. Themethod used is as follows:PAGE: 501. Select MODE 02. Program the CRTC for interlaced sync. and video.3. Set the EVNTV vector to point to your code.4. Enable the vertical synchronisation event.5. Use OSBYTE 70 (X=1 ) (*FX 112, 1 ) to select the half-frame to be drawn.6. Draw the half-frame.7. Use OSBYTE 70 (X=2) (*FX 112,2) to select the second half-frame.8. Draw the second half-frame.9. Use OSBYTE 71 (X=1,X=2) (*FX 113,1 and *FX 1 13,2) to select alternate screens on alternate vertical synchronisation events.The program will alternate the half-frames correctly but should provide thefacility to reverse the display sequence as the hardware may present the twohalf-frames in the incorrect phase.The display may be distorted if any software disables the verticalsynchronisation event.PAGE: 51OSBYTE &75 (1 17) is used to read the VDU status byte, and puts its currentvalue into the X register. The bits in the result have the following meanings.VDU status - bit 0 printer output enabledbit 1 scrolling disabledbit 2 paged software scrolling enabledbit 3 text window is currently defined this is set up by VDU 28 and cleared by VDU 26bit 4 shadow screen selectedbit 5 printing at graphics cursor enabledbit 6 cursor editing mode enabledbit 7 VDU is disabled via VDU 21.PAGE: 527 THE USER PORTThe User Port provides the following facilities:Eight-bit bi-directional dor applications 13580186 Error Messages 136Escape Processing 13880186 Monitor 13880186 OSWORD call 14215. Disc filing systems 145DFS 145ADFS 146CP/M Disc Format 14716. ANFS 148Local buffering 148Operating System Commands 149*HELP 149*CDIR 149*FLIP 149*FS 150*I AM 150*LCAT 150*LEX 150*PASS 150*WIPE 151Extra Utils star commands incorporated in the ROM 151*POLLPS 151*PROT 151*UNPROT 152*PS 152*WDUMP 152*CONFIGURE commands. 152*STATUS commands 153Extra *OPT commands 153Printing 154Extra interfaces 154Enhancements to the filing system interface 154Write only files 154OSFILE 155OSARGS 155Error messages 155User Root Directory Reference Point 156Compatibility with DFS based software 157Additional library functionality 157Time and Date 1571/0 processor address space 157Automatic Bootstrapping 157Re-tries 158File server / Bridge net number translation 158Detection of wrong versions and ANFS 158Entry of hexadecimal numbers 159Events on reception 15917. Terminal emulator 160OSBYTE 96,x 160Terminal File Transfer 16018. Editor 161Buffer Transfer 161From the language to Editor 161From EDITOR to the language 16119. VIEW and VIEWSheet format 162Reserved Characters and File Format 162VIEW formatting characters 162Memory Format 163Number Registers 164VIEWSHEET data representation 164APPENDICES Appendix 1 Differences between Model B+ and Model B 165Appendix 2 Differences between Master 128 and Model B/B+ 171Appendix 3 Differences between Compact and Master 128 190Appendix 4 - Differences between ANFS and NFS 200Appendix 5 Changes introduced in Basic 4 203Appendix 6 - PCB selection links and test points 205Appendix 7 Cartridge interface 210Appendix 8 65C12 Instruction set 215INDEX 283PAGE: 11INTRODUCTIONThis book is intended for peripheral hardware designers and software writersand expands the information given in Reference Manuals Parts 1 and 2It contains software and hardware reference material, with applicationguidelines which anyone who is attempting a major project for the first timewill find particularly useful. The remaining chapters contain information onthe Acorn-designed semi custom chips and a number of detailed appendiceshighlight the differences between the Master 128 and other Acorn modelsincluding the Compact and the Electron.It has been assumed that the reader has a good understanding of basicelectronics and computer terminology.PAGE: 12 1 THE MASTER SERIESARCHITECTUREIntroductionThe Master Series is based on and extends the architecture of the Acorn BBCModel B microcomputer The heart of the computer is a comprehensive machineoperating system (MOS) which controls and organises the communicationsbetween a central processing unit (CPU) and applications software, peripheraldevices. such as video displays and printers and filing systems which act assources and stores for data. Language interpreters and compilers may beprovided to convert high level languages into a format usable by the MOS.Alternatively, the applications may be in object code which runs directly onthe CPUThe simplest version of the computer (the Master 128) has a single processorwhich performs all of these executive functions In other computers of theseries, responsibility is split between a base processor which handlesinput/output(I/O) operations and a language processor which performs thecalculations and other data operations associated with the applications'tasks. In general, the language processor will be selected for its suitabilityfor a particular application and will be different from the base processor.Core MachineAll input/output (I/O) computing is performed by a 65C12 CPU ata port with optional handshakingProgrammable pulse generatorProgrammable frequency generatorPulse counterSynchronous/asynchronous SI PO/PISO shift registerIt appears as a set of memory-mapped locations and is accessed using OSBYTEs&96,&97 (150,151). As the parallel printer port is controlled by the same 6522versatile interface adapter (VIA) chip, care should be taken to avoid conflictsbetween the two applications. The 6522 registers that control the User Port aredescribed here, bit-by-bit. DO is the least significant bit, D7 is the mostsignificant bit. The User 6522 VIA has a base address of &FE60TimersTwo sixteen-bit counter/timers are provided. They are designated T1 and T2.Each consists of a sixteen-bit decrementing counter, one or two eight-bitlatches and some control logic. The latches are used to store the values thatwill be loaded into their respective counters when a particular event occurs.The modes of operation are determined by the Auxiliary Control Register.User VIA Address MappingOffset Function0 User Port Data Register2 User Port Data Direction Register4 T1 - Low Order Counter/Latch ( R/W)5 T1 - High Order Counter (R/W)6 T1 - Low Order Latch (R/W)7 T1 - High Order Latch (R/W)8 T2 - Low Order Counter/Latch (R/W)9 T2 - High Order Counter (R/W)10 Shift Register12 Peripheral Control Register13 Interrupt Flag Register14 Interrupt Enable RegisterPAGE: 53User Port Data RegisterUser Port access. Bit PB0 on the User Port corresponds to the data bit D0whilst PB7 corresponds to D7. Control lines CB1 and CB2 can be programmed tobehave as handshake lines. CB1 acts as Data Acknowledge. CB2 acts as DataReady. For example, if the following connections are made between two MasterSeries computers (A and B)Computer A Computer BPB[0:7] to PB[0:7] CB1 to CB2 CB2 to CB1Ground to Groundwhen the interrupts are enabled, writing a byte to the User Port in A willcause an interrupt to be generated in B. When B reads the data from its UserPort, A will be interrupted to indicate that the data has been taken. The datatraffic will also work in the other direction.The manufacturer's data sheet should be consulted for detailed timinginformation.User Port Data Direction RegisterEach bit in this register acts as a flag for the corresponding User Port bit.If set it will be an output, if clear an input.Timer 1 Low Order Counter/Latch (R/W)Read - the T1 low order counter is read and the T1 interrupt flag (in theInterrupt Flag Register) is cleared.Write - the data written into this latch is transferred to the T1 low ordercounter after either the T1 high order counter is written to, or the T2counter underflows through zero in the free-run mode.Timer 1 High Order Counter (R/W)Read - the T1 high order counter is read, but the T1 interrupt status is notaffected.Write - the data written into the latch is stored and transferred into the T2High Order counter at the next system 1 MHz high transition. T1 low orderlatch is transferred to T1 low order counter at the same time. This actioneffectively starts the counter and the T1 interrupt flag is clearedaccordingly.PAGE: 54Timer 1 - Low Order Latch (R/W)Read - the value in the T1 low order latch is read. T1 interrupt status is notaffected.Write - equivalent to writing to Offset 4.Timer 1 High Order Latch (R/W)Read - the last value written is read back.Write - the value written is stored, but is only transferred to the T1 highorder counter when T1 underflows in free-run mode.T2 Low Order Counter/Latch (R/W)Read - T2 low order counter is read and the T2 interrupt is cleared.Write - the data written is stored in the T2 low order latch.T2 High Order Counter (R/W)Read - T2 high order counter is read.Write - the data is written directly into the T2 high order counter. Thiscauses the value in the T2 low order latch to be transferred into the T2 loworder counter and the T2 interrupt is cleared.Shift RegisterA multi-function register controlled by the Auxiliwith its principalancillary components.128 Kbyte of dynamic random access memory (DRAM)Special expansion options allow a further expansion of 64 Kbyte.Dedicated hardware can be used to expand this almost indefinitely.262 Kbyte of read-only memory (ROM)Special expansion options allow a further expansion of approximatelyhalf a megabyte of ROM. Plug in cartridges are available which acceptup to 256 Kbyte of ROMPAGE: 13Internal I/OInternal versatile interface adapter (VIA)This services a 93-contact keyboard with two key rollover, a three channelsound generator with additional noise channel and a battery-backed real-timeclock with fifty bytes of RAM.External versatile interface adapter (VIA)This services the parallel printer port and the user portCo-processorsThese consist of an additional CPU with associated memory. They dependentirely on the main processor for all I/O operations.ExternaI I/OVideo displayA 6845 CRT controller formats the output for RGB, composite video andPAL/NTSC connectors.Analogue to Digital ConverterA four channel A-D converter provides ten bit binary conversions in 5ms. Theabsolute accuracy will depend on the conditions of useTape interfaceFacilities to both save and retrieve data from audio cassettesDisc InterfaceFacilities to both save and retrieve data from standard Shugart connectedmedia. Filing systems data encoded in FM or MFM format.Network InterfaceConnection to ECONET is provided by a 68B54 advanced data link controllerThis is fitted on a daughter board and may be an optional extra (standard onthe ET machine)1MHz BusStandard BBC computer 1 MHz bus.External Second ProcessorAn external second processor may be connected Selection of either internalco-processor or external second processor is performed by software Onlyone second or co processor can be active at a timeCentronics PrinterPort Connection for a standard parallel printerUser PortThe user port is an eight-bit bi-directional bus with two extrahandshaking/serial lines. These are unbuffered.RS423A serial RS423 port This is an enhanced version of the RS232CspecificationPAGE: 14Audio OutputThe output from the sound generator is amplified to a speaker and provided ata phono-style connector. Sound transfer to and from the modemModem Connection for a modem with both dial pulse and dual tone multi frequencydialling.Internal Input/OutputSlow peripheralsThese are subsystems which are provided with data from port A of the system VIAThis data is stable until next programmed by the CPUSound GeneratorThe sound generator is an SN7694A device, which generates three sound channelsplus one pseudo random noise channel The full description of it is found in themanufacturers data sheet. It receives a reference clock of 4MHz from centraltiming. The output can be connected by screened cable to the optional modemThis output is mixed on the modem board to generate dialling tones for DTMFexchanges where the modem hardware does not provide such tones itselfReal time clock with RAMA 146818 RTC and RAM chip is provided with battery backed supply The chipoperation is described in the manufacturers data sheet. There are three AA sizebatteries which normally keep the RAM backed-up for at least a year (dependingon how much the machine is NOT used)The keyboard mounted battery is charged whilst the computer is running from themains supply An over charge prevention circuit is provided with the followingaction:-a) Upon switch on, charging current of about 30mA is appliedb) After approximately 15 minutes the charging current falls to 1 mA.c) Trickle. charging continues at 1 mA for as long as mains power isapplied.The minimum charge burst is designed to provide battery back-up over a weekendafter just a few minutes operation. A 10mf capacitor is connected across theclock chip supply connections to prevent loss of data in the event ofaccidental battery disconnectionPAGE: 15Configuration StatusFifty bytes of CMOS RAM are available within the chip Twenty of these aary Control Register atOffset 11 . It is a left-shift, circulating register, i.e. data is shifted infrom bit 0 towards bit 7 and when shifting out, has bit 7 connected to theinput of bit 0. It has eight modes of operation which are in no way related tothe screen modes.Mode 0 - Static Shift Register.Read - the value shifted into the shift register is read.Write - the shift register will contain the value written.Shift - the data on CB2 will be shifted in on CB1 positive transitions.Interrupts - the shift register interrupt is disabled.Mode 1 - Data Shifted in by T2.Read - the value shifted into the shift register is read. Shifting will start.Write - the shift register will contain the value written. Shifting will start.PAGE: 55Shift - data is shifted in on CB2a) after a read/write operation with the SR interrupt clear,b) after T2 times out following a read/write with SR interrupt SET. Shiftingwill occur for eight T2 time-outs.Interrupts - the SR interrupt will occur after eight T2 time-outs.Note: In this mode CB1 is clocked with the T2 time-out. This is to provide aclock for the external device providing the data. Data is shifted in on the CB1negative edge, but is sampled (latched) on the CB1 positive edge. For thisreason, the external device should be clocked on the CB1 negative edge.Shifting stops after the eighth shift.Mode 2 - Data Shifted in by the system 1 MHz clock.This is similar to Mode 1 except that CB1 clock is the system 1 MHz clock,divided by two.Mode 3 - Data Shifted in by externally provided CB1 clock.This mode is used when data is provided by an asynchronous source from which aclock is derived.Read - the value shifted into the shift register is read.Write - the shift register will contain the value written.Shift - data is shifted in on CB2 at the system 1 MHz pulse after the CB1positive transition.Interrupts - the shift register interrupt is set after 8 data bits have beenshifted in. It is reset at the next read/write of the shift register.Note. Due to the shift-in timing, it is recommended that the incoming data rateshould not exceed 250kHz, thereby allowing for the asynchronism between thetransmitting and receiving units. The actual data rate is more likely to belimited by the speed with which the 'register full' interrupt is serviced; theshift register keeps shifting whether or not it is serviced, so data may belost if the user's program does not respond in time.Modes 4 and 5 - Data Shifted out by T2.Read - the current shift register value is read. Shifting will start.Write - the shift register will contain the value written. Shifting will start.Shift - data is shifted out on CB2a) after a read/write operation with the SR interrupt clear.b) after T2 times-out following a read/write with S R interrupt set. In Mode 4,shifting occurs at every T2 time-out. In Mode 5, shifting will occur for eightT2 time-outs and then stop until the interrupt is serviced and new data isloaded. Interrupts - the SR interrupt will occur after eight T2 time-outs.PAGE: 56Note: In this mode CB1 is clocked with the T2 time-out. This is to provide aclock for the external device sampling the data. Data is shifted on the CB1positive edge, but should be sampled by the external device on the CB1 negativeedge. For this reason, the external device should be clocked on the CB1negative edge. Shifting stops after the eighth shift in Mode 5 but iscontinuous in Mode 4.Mode 6 - Data Shifted out by the system 1 MHz clock.This is the shift out equivalent of Mode 2.Mode 7 - Data Shifted out by externally provided CB1 clock.This is the shift out equivalent of Mode 3. The same restrictions to data rateapply.Auxiliary Control Register (R/W )Controls the shift register mode, Timer 1 . Timer 2 and the Port A B latching.It is divided into three fields(1) Port LatchingBit 0 enables/disables latching of the Printer port. This bit must bemaintained at all times.Bit 1 enables/disables latching of the User Port. A logic 1 will enablelatching. CB1 acts as a strobe re usedby the operating and filing systems for initial configuration of the hardware.Of the remainder ten are reserved for future use by ACORN, ten are for 'thirdparty' use and the remainder are for the userClockThe clock operates from a 32 768KHz crystal oscillator A trimming capacitor isprovided as is a test point with the buffered clock output. Year month. dayhour minute and second information is provided with automatic leap year (butnot automatic leap century) correction. An alarm is also included within thechip, but there is no operating system support for this facility. An optionalnlRQ connection can be made to the CPU from the clock chip, enabling the alarmto change program flow.Operation of the clock chip in this manner involves direct manipulation of thechip control signals and should only be attempted by competent programmers.Acorn Computers are not responsible for incorrect programming by theuser/software supplier.If power is removed during an access to this chip, the chip select will becomeinvalid, with the possibility of write accesses being corrupted. This isavoided by inverting the chip select with a transistor whose collectorresistor is connected to the battery backed supply. As power fails to the maincircuitry the transistor base current reduces and the transistor switches offdeselecting the chip.1MHz Internal I/OVarious devices operate at a 1MHz bus rate. Only one internal I/O componentworks at this speed - the system VIA.System VIAA 6522 allows several sources to create maskable interrupts. The sources are:-a) CRTC vertical synchronisationb) A D converter; end of conversion signal.c) CRTC light pen strobe.d) Keyboard key detectIt also provides the slow data busPort B on this device generates and reads a number of internal hardware strobesPAGE: 16These are:-Port B Data Strobe Active LevelPort B Data Strobe Active LevelD7 DODXXXXXXX Clock Address HXDXXXXXX Clock chip enable HXXDXXXXX 'Fire' button 1 InputXXXDXXXX 'Fire' button 2 InputXXXXD000 Sound chip select LXXXXD001 Clock R/W LXXXXD010 Clock Data QXXXXD011 Keyboard enable QXXXXD100 CO Screen control LXXXXD101 C1 signals HXXXXD110 Caps Lock indicator LXXXXD111 Shift Lock indicator LNote: Q is the value of D after the port write operation is completed2MHz Internal I/OOnly one internal I/O component operates at this clock rate, the internalsecond processor TUBE. Its data bus is connected directly to the CPU databus. The second processor interface will only be specified as a hardware datatransfer definition. In this way, the actual second processor used will not beconstrained by this specification.The interface is a parallel port providing the following data access signals:-i) DO to D7 A bi-directional bus to TTL levels.ii) AO to A2 A uni-directional bus to CMOS levels.The following control and timing signals are provided:- HostCPU phi2 CMOS levels System Reset TTL levels HostCPU nlRQ This must be an 'open collector' node with an active low TTL level 8MHz timing reference TTL levels TUBE chip select CMOS levels Read/Write TTL levelsPAGE: 17External Input/Output1MHz External I/OAnalogue PortThis 15-way D-type connector provides access to an NEC mPD7002 four-channel,ten-bit analogue-to-digital converter. The sampled input is compared to a 1.8Vreference derived from three small signal diodes in series.A tracked link may be cut to deselect this reference. The user may then solderin a two-pin precision reference in the holes provided or supply an externalreference. Any user supplied reference should have a maximum voltage of 2.5V.An input voltage on any one of the four channels will be digitised when the AIDcontrol register is so instructed. Conversions are in the range 0 to 1.8V.The voltage reference is made available at the connector. Provision is madeon the board for an additional high stability reference, if required. A linkwill have to be made for the additional to latch the data.(2) Shift Register ControlBits 4,3,2 Function 0 0 0 Mode 0 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7(3) Timer 2 ControlBit 5 0 - interrupt when T2 decremented to zero1 - decrement T2 with each pulse input to PB6. Interrupt when T2=0,then re-load and continue counting, so generating an interrupt stream.T2 high order counter must be written after every T2 interrupt to enablethe next interruptPAGE: 57(3) Timer 1 ControlBits 6,7 Operation0 0 After loading T1 , it will generate a single interrupt after decrementing to zero.0 1 After loading T1 , it will generate a stream of interrupts; one whenever it counts down to zero.1 0 As 00 but output a single pulse on PB7 as well as the interrupt.1 1 As 01 but generate a stream of output pulses as well as the interrupts,Note: When Timer 1 mode 1 1 is selected, PB7 will change polarity every time T1counts down to zero. This means that it will output a waveform of frequency.PB7 frequency = 1/(*2)Peripheral Control Register.The most significant nibble dictates the function of the CB1, CB2 controllines, whilst the least significant nibble controls CA1, CA2. The lattershould not be touched as it may interfere with correct parallel printeroperation. Whenever writing to this register, ensure that the leastsignificant nibble is preserved.CB1 Interrupt ControlBit 4 0 - generate an interrupt on a CB1 negative edge. 1 - generate an interrupt on a CB1 positive edge.CB2 ControlBits 5,6,7 Operation0 0 0 CB2 will generate an interrupt on its negative edge0 0 1 CB2 as above, independent mode0 1 0 CB2 will generate an interrupt on its positive edge0 1 1 CB2 as above, independent mode1 0 0 CB2 provides the 'Data Ready' handshake output.1 0 1 CB2 provides a single high-going pulse.1 1 0 CB2 goes to a 01 1 1 CB2 goes to a 1Independent ModeWhilst reading the User Port Data Register would normally clear the interruptrequest that transitions on CB2 have created, in the 'independent modes' theseinterrupts have to be cleared by directly clearing the appropriate bits in theInterrupt Flag Register.Note that the bits 0, 1 ,2,3 perform a similar function for CA1 and CA2.PAGE: 58Interrupt Flag RegisterThe CPU has to be able to determine which function of the User Port isgenerating an interrupt. This register has a bit representing each of thefunctions that can do this. Even if an interrupt source has been disabledusing the Interrupt Enable Register, it can still set its appropriate flag inthis register. A set bit indicates that the function is trying to generate aninterrupt.Register bit set when... cleared when...0 CA2 active edge occurs Printer port is accessed1 CA1 active edge occurs Printer port is accessed2 Shift Register completes Shift Register is accessed 8 shifts3 CB2 active edge occurs User Port Data is accessed4 CB1 active edge occurs User Port Data is accessed5 T2 times-out Read T2 low order OR Write T2 high order6 T1 times-out Read T1 low order OR Write T1 high order7 Any interrupt is set All interrupts are clearNote that bit 7 is designed to enable fast interrupt control. It is onlynecessary to test bit 7 to find out if any of the functions are generating aninterrupt request. The CPU's BIT operation will cause its negative status bitto be set if bit 7 is set in this register.Interrupt Enable RegisterFor each bit in the Interrupt Flag Register to cause an interrupt, thecorresponding bit in the this register must be set.Register bit Enables the interrupt from0 CA21 CA12 Shift Register3 CB24 CB15 Timer 26 Timer 17 GlobalIf the Global bit is clear, then every set bit in the register disables thecorresponding interrupt request. If it is set then every set bit in theregister enables the corresponding interrupt request.When this register is read, Bit 7 will be set and other bitsreference to be used. Conversionstake place in 5ms and the 'end of conversion' pulse causes an IRQ to begenerated by the system VIA.Two fire buttons are provided for with the connections I0 and I1. These areconnected to the system VIA and cause interrupts (as IRQ ) to be generated.Light PenA light pen may be connected to the signal LPSTB. This also causes the systemVIA to generate an IRQ (if enabled). It also causes the 6845 CRTC to latch theaddress of the currently selected video data byte. This may not be the same asthe displayed byte and some software correction may be necessary. Factors suchas phosphor characteristics, light pen response and the angle at which the penis used, may all affect the correction needed.2MHz External I/OTwo peripheral devices operate at 2MHz. These are the external second processorconnection and the ECONET connection.External Second ProcessorThis interface has a buffered data bus via the Peripheral Bus Controller(PBC). TheEXbus on this component provides for good data set up and hold times. Togetherwith a limited degree of line matching, this ensures reliable high speed datatransfer.PAGE: 18 with unspecified cable lengths. A maximum cable length of one metre issuggested to prevent noise problems.The interface operates at 2MHz. This means that if a 1 MHz bus peripheral isalso connected, then the address and data buses on this connector will appearto perform both 1 and 2MHz cycles.The connections are:-DO to D7 Data Bus CMOS levelsAO to A7 Address Bus TTL levelsIRQ Interrupt Request Open collector TTL levelsnTUBE Parasite chip select TTL levelsSupply +5VGround 0VPAGE: 192 CIRCUIT DESCRIPTIONThis chapter should be read in conjunction with the circuit diagram at therear of this manual.The microprocessor used in the Master 128 is a 65SC12 running at either one ortwo megahertz clock rate. Most processing is done at 2MHz, including accessesto the Random Access Memory and Read-Only Memory. The processor slows downto 1MHz when addressing slow devices such as the 1MHz Extension Bus, theAnalogue to Digital converter and the Versatile Interface. A 16MHz crystaloscillator provides clock signals for the microprocessor in conjunction withdivider circuitry on the video processor (VIDPROC) uncommitted logic arraychip (IC42) which produces 8, 4, 2 and 1 MHz signals.Random Access Memory on the microcomputer is provided by four 4464 dynamicmemory devices (ICs 17,18,23,26). Row-address and column address strobesignals for these RAMs are generated from the 8, 4 and 2MHz clock signals.These RAMs are cycled constantly at 4MHz. Two devices may have control of theRAM address lines, one is the 65SC12 microprocessor and the other is the 6845cathode ay tube controller chip (IC22).The CRTC generates the raster scan signals for the video display, togetherwith the address for each memory-mapped byte of information in the RAMs whichis required to refresh the display. An MSI CRTC multiplexer (IC31 ) switchescontrol of the RAM address lines between the microprocessor and the CRTC.The 65SC12 microprocessor is particularly suitable for this kind ofapplication, because it runs from a constant clock, d2, and so itsrequirements for memory access are predictable. Every 250ns, control of theAM address lines is switched between the microprocessor and the CRTC. Thus, ina one microsecond period, the microprocessor has two RAM accesses and the CRTChas two RAM accesses.Because the CRTC generates a sequence of addresses in order to refresh thedisplay, the row address lines of the RAMs are constantly cycled. Carefuldesign of the addressing methods in each screen mode ensures that the dynamicRAMs are also refreshed by the sequential CRTC accesses.Using this technique, two bytes of information are available per microsecondfor refreshing the raster scanned video display. With each horizontal linehaving a period of 64ms, a 40ms active display area is usual. Thus, 640 bitsof information per horizontal line are produced from the memory will be aswritten.PAGE: 59Example of motor controlFor example, to control a three axis machine which uses stepper motors, Timer 1frequency generator output may be used to provide stepping pulses to motorphase sequence generators. Other PB lines can provide forward/backward controland move/hold controls. This means that all three motors can be rotating atonce. The Timer 2 pulse counter can be used to count the number of pulses thathave been applied to the motors. Every time a T2 interrupt is generated, thosemotors which are enabled will have their positions (as stored in memory)updated by the CPU. Limit switches on each axis can be connected to over-ridethe 6522 outputs and logically ORed to generate an interrupt so that if anymotor tries to go 'off the end' the CPU will detect this and so prevent theoccurrence of any damage. The PB lines can then be used as inputs to determinewhich motor has gone to its end stop.MethodAssign the User Port pins :a) CB1 will be the global alarm (overrun) input.b) PA7 is the frequency generator output.c) PA6 is the pulse counter.d) PA5 is the Z axis enable/fault indicator.e) PA4 is the Z axis direction control/fault indicator.f) PA3 is the Y axis enable/fault indicator.g) PA2 is the Y axis direction control/fault indicator.h) PAl is the X axis enable/fault indicator.i) PA0 is the X axis direction control/fault indicator.To run the motors:PA7 must be a frequency outputPA6 must be a counter inputPA[0:5] must be outputsThus.Location Contents Comments 7 0&FE6A 0000oooo CB1 negative interrupt&FE6B 1110oooo Set up the timer controls&FE6E 1ooo1ooo Enable the T2 interrupt&FE62 10111111 Enable the outputs&FE60 XXDDDDDD Operate the motorso is the old contents D is the desired actionPAGE: 60Timer 1 should be programmed with the value for the required operatingfrequency.To find out which motor has overrun:PA[0:5] should be inputsPA7 should be switched off whilst the overrun is checked.Thus:Location Contents Comments 7 0&FE6B 0010oooo Switch off Timer 1&FE62 10000000 Inputs to read the switches.&FE60 XXDDDDDD Read the switches.o is the old contents D is the desired actionOperation can now be returned to 'Running Mode'.PAGE: 618 THE SERIAL PROCESSORThe serial processor (SERPROC) is used in conjunction with the 6850 UART toprovide the RS423 and cassette tape interfaces. It contains a baud rategenerator, channel multiplexer and tone generator.UARTThe device responsible for providing most of the serial port functions is a6850 UART. This has all the receive/transmit and data formatting/error checkingthat is necessary for both systems. It is fully described in the March 1983edition of the Hitachi Microcomputer Databook.SERPROCThe ACORN proprietary part, SERPROC is effectively a multiplexer and baud rategenerator for the 6850. It also generates the phase-continuous transmissioncircuitry for use with the cassette interface.Buffer ComponentsThe RS423 transmit data and CTS lines are buffered by an AM26LS30 orequivalent. This provides a single ended transmission with slew rate limitedoutput. RS423 receive data and RTS is buffered by a mA9637AC or equivalent.Both buffers are connected with single-ended input configurations.Cassette data output from the SERPROC is buffered by a single, non-invertingoperational amplifier with a simple single pole filter, a.c. couplingcapacitor and current limiting output resistor.PAGE: 62Control Register Settings Bit # Function Parameters 0-2 Transmit Baud Rate 000 : 19200 100 : 9600 010 : 4800 110 : 2400 011 : 1200 101 : 300 011 : 150 3-5 Receive Baud Rate 000 : 19200 100 : 9600 010 : 4800 110 : 2400 011 : 1200 101 : 300 011 : 150 111 : 75 6 Channel Select 0 : Select Tape 1 : Select RS423 7 Cassette Motor Relay 0 : Contacts open 1 : ContactsNote. The Transmit and Receive baud rates b-mappeddisplay. The video processor VIDPROC (IC42) is a custom uncommitted logicarray developed by Acorn. At the end of each CRTC 250ns access period, itlatches the byte from thePAGE: 20RAM and, according to the display mode in operation, serialises the byte intoa one-bit stream of eight bits or a two-bit stream of four bits etc. In thisway, display modes varying from 640 pixels in 2 colours to 160 pixels in eightcolours, which may be flashing, can be produced.The video processor also contains a high speed block of static random accessmemory called a palette. This memory can be programmed to define therelationship between the logical colour produced by the RAM and the physicalcolour which will appear on the display. Thus, in a 640 pixel mode, the twocolours to appear on the display need not be black and white, they may be,say, red and blue. The information in the RAM is unchanged by the palette. itis its interpretation into physical colours which changes.Modes 0-6 in the microcomputer use software-generated characters, that is tosay, the character font to be produced on the screen is held in the memorymapped display area of the RAM and graphics or characters may be held. Thismethod of producing characters is expensive in memory, involving a minimum ofeight kilobytes for the display memory.Display Mode 7 is a Teletext mode implemented by an SAA5050 (IC32) Teletextcharacter generator. IC15 latches the information coming from the RAM prior tothe SAA5050. When using this mode, only 1 K of RAM is devoted to the displaymemory and the characters are held within it as ASCII bytes. The SAA5050 thentranslates these bytes into a standard Teletext/Prestel format display.The red, green and blue logic signals produced by the video processor arebuffered by MSl CH ROMA chip ( lC40) and fed out together with a compositesync signal to the RGB connector. This output is suitable for feeding straightto the gun drives of RGB monitors. The red, green and blue lines are summed bybinary weighted resistors to feed Q13 which produces a 1v composite videosignal suitable for feeding to monochrome monitors, on which the differentcolours will appear as different shades of grey.A modulator provides a UHF TV signal on channel 36, suitable for feeding to theaerial input of a domestic television receiver. Colour is derived from a PAL(phase alternating line) encoder circuit which modulates the colourinformation on to the colour subcarrier frequency. Q10 is a 17.73MHzoscillator circuit which is divided by a ring counter (IC46) giving an outputat the colour subcarrier frequency of 4.43361875MHz which is fed to IC40. Thisselects different phases of the 'U' and 'V' signals according to whether ared, green, blue, cyan, magenta, yellow or white colour is to be produced.These signals produce the colour subcarrier signal which is added to themonochrome output from Q8 by the buffer Q9. A reference colour burst isprovided at the beginning of each line for the receiving televisionto interpret the colour information.PAGE: 21The PAL signal may be added to the 1 v video connector by the insertion of a470pF capacitor between the emitter of Q9 and the base of Q7.Resistors R132-4 adjust the luminance balance of the colours.Memory provision comprises four 4464 dynamic RAM chips (IC16, 17, 23, 26)which give 128 kilobytes of storage and a one megabit ROM ( IC24) mapped aseight 16K blocks,INPUT/output is under the control of an MSI I/O controller IC15. This isconnected directly to the control lines of the executive chips responsible forperipheral access.One 6522 VIA device (IC9) is devoted to internal system operation. Port Bdrivesan addressable latch which is used to provide read and write strobe signalsfor the speech interface, the keyboard and the sound generator chip. Alsocoming from this latch (IC 32) are control lines C0 and C1 which indicate theamount of RAM devoted to the display memory to be 16K, 8K, 10K or 20K. Pins 6and 7 of the addressable latch drive the caps lock and shift lock LEDs on oth assume that the 6850 has itsclock divider set to divide by 64.Receive baud rate not used in cassette mode, but Bit 3 may control inversionof the Transmit data (VTI version of SERPROC)PAGE: 639 THE PERIPHERAL BUS CONTROLLERThe peripheral bus controller buffers data between the 65C12 CPU con the 'CD'bus) and the internal peripherals on the 'BD' bus, the external '1 MHz Bus'and the external 'Tube' interfaces (both on the 'ED' bus). It also contains atimer to generate a long delay after power-up.Internal TimingAll the necessary timing is synthesised from the system 8MHz and 1 MHz signals.Buffer ControlThe selected buffer path is determined by the RDY and FIT signals, as describedfor the I/O Controller, together with the system R/W signal.TimerThe timer is an eight-bit counter with an external oscillator, which is alsoused as the timer's output. The oscillator output is used to charge/dischargea timing capacitor. The use of a charge time constant which is 1% of thedischarge time constant causes the output (CHRG) to be low most of the time.When the input (TICK) crosses the threshold during an oscillation, the counteris incremented. When the terminal count is reached, the output is fixed high.The counter can only be reset by switching the power off. This timer wasoriginally designed to support the boost charge of nickel-cadmium batteriesfor the Real Time Clock.PAGE: 64I/O DefinitionPin Name No I/O Input Buffer Type Output Buffer TypeTICK 4 I CMOS SCHMITTNFIT 5 I CMOSR/W 6 I CMOSRDY 11 I CMOSNPRST 1 I TTL -DEN 2 I TTL -M1 29 I TTL -M8 31 I TTL -CHRG 3 0 - standardBRNW 7 0 - standardEM1E 8 0 - standardER/W 9 0 - standardED7 12 I/O TTL standard + tristateED6 13 I/O TTL standard + tristateED5 14 I/O TTL standard + tristateED4 15 I/O TTL standard + tristateED3 16 I/O TTL standard + tristateED2 17 I/O TTL standard + tristateED1 18 I/O TTL standard + tristateED0 19 I/O TTL standard + tristateCD7 28 I/O TTL standard + tristateCD6 27 I/O TTL standard + tristateCD5 26 I/O TTL standard + tristateCD4 25 I/O TTL standard + tristateCD3 24 I/O TTL standard + tristateCD2 23 I/O TTL standard + tristateCD1 22 I/O TTL standard + tristateCD0 21 I/O TTL standard + tristateBD7 40 I/O TTL standard + tristateBD6 39 I/O TTL standard + tristateBD5 38 I/O TTL standard + tristateBD4 37 I/O TTL standard + tristateBD3 36 I/O TTL standard + tristateBD2 35 I/O TTL standard + tristateBD1 34 I/O TTL standard + tristateVCC 30 Vcc connection (low inductance)GND1 10 Primary GND connection (low inductance)GND2 32 Secondary GND connection (low inductance)GND 3 20 Secondary GND connectionPAGE: 65AC Parametric Test Information - Timing SpecificationsTiming Point to point Parametric-Specification Time(ns) Output LoadSymbol measured at Vcc=Min Tamb=Max Min Max I/Face ValueTj1 M1 (LH/HL) jitter wrt M8 (HL) -30 +4Td1 EM1E (LH/HL) from M8 (HL) 0 60 TTL ATd2 ER/W (LH/HL) from RNW (LH/HL) 0 80 TTL ATd3 ER/W (LH/HL) from M8 (HL) 0 70 TTL ATd4 BR/W (LH/HL) from R/W (LH/HL) 0 50 TTL BTd5 CD7..0 stable data from NFIT (HL) 0 85 TTL CTe2 BD7..0 (ZH/ZL) from M8 (LH) 0 90 TTL BTz2 BD7. . 0 (HZ/LZ) from M8 (HL) 0 72 Z BTd6 B Bus , SA to SL data, from M8 (HL) 0 75 TTL BTd7 B Bus , SL to SA data, from M8 (LH) 0 90 TTL BTe3 ED7..0 (ZH/ZL) from NFIT (HL) 0 90 TTL ATz3 ED7. .0 (HZ/LZ) from M8 (HL) 0 105 Z ATz4 ED7..0 (HZ/LZ) from NFIT (LH) 0 105 Z ATd8 CD7. . 0 (LH/HL) from BD7 . .0 (LH/HL) 0 70 TTL CTd9 CD7. . 0 (LH/HL) from ED7. . 0 (LH/HL) 0 70 TTL CLoad circuit component values Load Value C(pf) R(ohms)For details of load circuit A 150 1000see AC measurement definition B 100 1000 C 170 1000Drawinthekeyboard.The rest of Port B on the internal system VIA is used to input the two 'firebutton' signals from the analogue to digital converter interface and tocontrol a real-time clock/CMOS RAM chip. Each time the system VIA is writtento, any changes on Port B which should affect the addressable latch arestrobed into the latch by a flip flop which is triggered from the 1 MHz clocksignal. Port A of the system VIA(IC9) is a slow data bus which connects tothe keyboard, the RTC/CMOS RAM chip and the sound generator. Port B is theunbuffered User Port.IC18 is a four channel sound generator chip which may be programmed to givevarying frequency and varying attenuation on each channel. An extra analogueinput from the 1 MHz extension bus is added to the sound generator signal andthen filtered by a quad operational amplifier (IC17). IC19 provides audio poweramplification to drive a speaker,Two forms of serial interface are provided, one is an audio cassette at either300 or 1200 baud and the other is RS423, over a whole range of baud rates.RS423 is electrically compatible with RS232C in most applications.)A 6850 asynchronous communications interface adaptor (IC4) is used to bufferand serialise or deserialise the data. A second ULA (SERPROC) is used in theserial interface, (IC7). Contained within this ULA is a programmable baudrate generator, a cassette data/clock separator and switching to select eitherRS423 or cassette operations. IC42 divides the main board 16MHz clock by 13and this signal is divided further within the serial interface ULA to producethe 1200 Hz cassette signal.PAGE: 22Automatic motor control of an audio cassette recorder is achieved by a smallrelay driven by a transistor from the serial interface ULA. The signal out ofthe cassette is buffered and the incoming signal is suitably filtered andshaped by a three stage amplifier. This is a quad operational amplifier(IC35). The RS423 data in and out signals and request-to-send andclear-to-send signals are interfaced by ICs 74 and 75 which translate betweenTTL and standard RS423/232 signal levels. This is one of the few sections ofcircuitry on the Microcomputer which requires an additional -5v supply to bepresent.A four-channel analogue to digital converter facility is provided by a mPD7002IC73. This device connects straight to the microcomputer's data bus and it is adual slope converter with its voltage reference being provided by the threediodes, D6, D7 and D8.Connection is made to the ECONET by a five way DIN connector mounted on themain circuit board. The interface electronics including the 68B54, linedrivers, receivers and chatter disconnect components are mounted on a separatecircuit board. This board has two connectors:-a) A 5-way connector which has a one-to-one connection with the DIN connector.b) A15-way connector provides the CPU data bus together with address, timing reference, chip select and interrupt signals. The main PCB has two further address connections for future expansion.A 6854 Advanced Data Link Controller circuit handles the Econet protocol. Datato be transmitted onto the network is fed from the ADLC to the line drivercircuit which produces a differential signal drive to the Econet cables.Received data is detected and converted to a logic signal by one half of IC94which is a dual compare circuit type LM319. The received data is then fed backto the data link controller circuit.An Econet installation has a external master clock station which controls thetiming for the network. This clock signal is transmitted around the network asa second differential line signal and it is used to clock the data in and outof the data link controller circuits. The network clock is also detected usingone half of the LM319 comparator IC4 and the detected clock is then fed to bothreceive clock and transmit clock inputs on the 6854. In the presence of anetwork clock, the monostable circuit, IC2 is permanently triggered and thisprovides a data carrier detect signal for the data link controller chip.g not reproducedPAGE: 66SA data latching point.The video data for the SA5050 Teletext Display device is time divisionmultiplexed with the internal 1MHz peripheral data (as distinct from theexternal 1 MHz Bus). This data is latched at the point X in the timingillustrated below.Drawing not reproducedSL data latching pointData for 1 MHz internal peripherals is latched at the point Y on the timingdiagram below.Drawing not reproducedPAGE: 67C Bus Drive WaveformsThe peripheral bus controller drives the CPU data bus (the C Bus) on thefollowing occasions: a) Reading from internal peripherals b) Reading from the external 1MHz Bus c) Reading from the external TubeBecause these events may or may not be in phase with the CPU cycle, the PBC withholds the data until the correct time.Drawing not reproducedReading from the 1MHz Bus or an internal 1MHz peripheral. EM1E is in phase.Drawing not reproduced Reading from the 1MHz bus or an internal 1MHz peripheral. EM1E is early.Drawing not reproducedPAGE: 68B Bus Drive WaveformsThe B Bus contains both the internal 1 MHz peripheral data and the SAA5050video data. This bus is used by the Modem connector, so it IS important toobserve the timing constraints.Drawing not reproducedPAGE: 69E Bus Drive WaveformsThe E Bus operates at either 1MHz or 2MHz under the control of the CPU READYline, which it samples. This signal is driven by the 1/O controller with alogic low to slow the CPU down to 1 MHz when a slow access is made. The PBCextends its bus cycle time in much the same way as the CPU. In this way the1MHz Bus and Tube connectors can be driven by the same buffer. It is importantthat 1 MHz Bus peripherals using any significant length of ribbon cable(greater than 30cm) use 2k pull up/down resistors to minimise line reflectionsto the Tube.Drawing not reproducedCase 1 - Writing to the tube.Drawing not reproducedCase 2 Writing to the 1MHz BusBoth of the two possible timing relationships are shown. The data has a nominal250ns data setup time before the rising edge and a minimum hold time of 125nsafter the falling edge of EM1E (measured at the PBC). The address set up isalso shown. This is generated by a latch clocked at 4MHz and so presents aminimum address set up time of 250ns and a minimum address hold time of 250ns.Drawing not reproducedPAGE: 7018 THE 1MHz BUSThis chapter describes the signals available on the 1 MHz Bus, the circuitryrequired to utilise them, and the way in which they are connected to the AcornExpansion Box. The expansion memory map is also defined. When interfacingdesigns to the 1 MHz Bus, it is vital to ensure compatibility with Acornstandards, to prevent problems when using several pieces of equipment on thebus simultaneously.The standards cover both hardware and software protocols. It is as importantfor the software to follow these guidelines as it is for the hardware,otherwise simultaneous operations of several peripherals may not be possible.The standards described allow up to 64K of paged address space to be accessedas well as 255 bytes of direct access ports.Signal definitionsThe following lines are available on the 1 MHz Expansion Connector.A0-A7 The low eight address lines from the 6502, buffered by a74LS244 (IC 71) permanently enabled.DO- D7 A bi-directional data bus connected to the CPU throughIC 72, a 74LS245 buffer. The direction of data isdetermined by the system Read-not-write (R/W ) line. Thebuffer is only enabled if nPGFC or n PGFD is low (seebelow).Analogue in An input to the BBC Microcomputer audio circuitry. Inputimpedance is 9K. A signal of 3volts RMS will produce asaturated signal at the loudspeaker (full volume), thoughsignals this large will cause distortion if the on-board soundor speech is used at the same time.nRST Not Reset. This is an OUTPUT ONLY for the system resetline (active low). It may be used to initialise peripherals onpower-up and when the 'BREAK' key is pressed.nPGFC & nPGFD 'Not page FC' and 'Not page F Oncethe network clock is removed, the monostable immediately drops out and thedata carrier is no longer detected.Econet is a broadcast network system on which a number of stations may attemptto transmit their data over the network at any given time. In this case, acollision can occur. the transmitting station detects the collision and backsoff before attempting to try again to transmit over the network. Collisionarbitration software isPAGE: 23included in the Econet system. Collisions on the network data lines result inthe differential signal on the two data wires being reduced and this conditionis detected by IC95 which is another dual comparator circuit.When there is a good differential data signal on the network one output ofIC95 or the other will be low, in which case the output of IC91 Pin 6 will behigh, indicating no collision. When there are no collisions on the network,and the network clock is detected by the clock monostable, the data linkcontroller is clear to send data over the network.When there is a collision on the network both outputs of IC91 will go high andthe clear to send condition will cease. Note that when the computer is notconnected to the network a collision-like situation results, in which caseagain the data link controller will not get a clear to send condition.Each Econet system requires termination at the two extreme ends of the networkwith network terminator boxes. It also requires an external network clock box.The network clock generates a 6MHz signal which is divided by two to produce3MHz and other clock rates down to 75KHz. The setting of this clock signaldepends on the length of the network, with the longer networks requiring aslower clock.Up to 255 stations may be connected to each Econet with each station beingidentified by a unique station identification number. This station ID isprogrammed into the battery-backed CMOS RAM. The data link controller circuitproduces interrupts which are fed to the central processor NMI line. Theseinterrupts are enabled every time the station ID is read. Once in the datalink controller interrupt service routine the DTR output of the ADLC goes lowin order to remove the interrupt.IC78 is a WD1770 or WD1772 floppy disc drive controller circuit which is usedto interface to one or two single or double sided 5 or 8 inch floppy discdrives. Logic signals from the controller to the disc drive are buffered byIC1. The incoming signal from the disc drive is first conditioned bymonostable IC87 producing a pulse train with each pulse of fixed width. Thesepulses are then fed to the data separation circuits ICs 81 and 82. This is adigital monostable. IC86 divides the 8MHz clock signal down to 31.25 KHz. ICs83, 84 and 85 are then used to detect index pulses coming in from the drivewhich show that the drive is ready for a read or write operation.IC69 is a versatile interface adaptor. Port A is used to provide a centronicsstandard parallel printer interface, with the octal buffer IC70 being used tobuffer the data lines. Port B is left uncommitted and is free for use by theuser for input or output purposes.PAGE: 24The address and data lines A0-A7 and D0-D7, together with some page selectlines are available as the 1 MHz extension bus to which various peripheraldevices, such as Teletext interface, may be connected. All accesses to thisbus will be at 1 MHz processor speed. The octal buffer DXXXXXXX and the octaltransceiver DXXXXXXX are used to interface these signals to the internal dataaddress bus.Selected address and data lines are available on the Tube connector which isused to connect second language processors into the system.KeyboardNinety-three keys are provided, ninety-two of which are in a modified 8x13matrix. A keyboard encoder, KBDENC (IC16) is used to scan the keyboard. Duringidle (free run) mode, pressing any key will cause an IRQ to be generated viathe system 6522. A connection is provided from IC16 to a 6522 'CA' typeconnection. Hence the interrupts thus generated are controlled by thD'. Page select signalsdecoded from the top eight address bits of the system databus. These signals are active low. Pages FC and FD (i.e.&FC00 to &FCFF and &FD00 to &FDFF) are the onlypages available for general expansion. However, thePAGE: 71paging register described in Section 5 allows a muchlarger address space to be accessed.nIRQ Not Interrupt Request (active low). The system IRQ linewhich is open collector (i.e. 'wired-or') and may beasserted by devices attached to the extension bus. Thepull-up resistor on this line is 3K3. 1 RQ is level triggeredand it is absolutely essential for correct operation of themachine that interrupts do not occur until the software iscapable of dealing with them. Interrupts on the 1MHz busshould therefore be disabled on power-up and resetconditions. Significant use of interrupt service time mayaffect other machine functions. In particular, maskinginterrupts for more than 1 OmS will affect the real timeclock.nNMI Not Non-Maskable Interrupt (active low). The system NMIline which is open collector (i.e.'wired-on') and may beasserted by devices attached to the extension bus. Thepull-up resistor on this line is also 3K3. It should beremembered that NMI is negative-edge triggered and thatboth the disc and net chips on the main board use this line.Caution must be exercised to avoid masking otherinterrupts by holding the line low. Use of NMI facilities onthe BBC machine requires an advanced knowledge of65O2 programming techniques and the Operating SystemProtocols.1 MHzE A system clock timing signal which is a 1 MHz 5O7% duty-cycle square wave. During access to 1 MHz peripheralsand to the extension bus the processor clock (normally2MHz) is stretched so that the trailing edges of 1MHzE andprocessor clock are coincident.R/W The system Read-Not-Write signal which is derived fromthe CPU R/W signal through two 74LSO4 inverters..0V System OV, i.e. GND wires, dispersed so as to interleavewith asynchronous groups of signals in a flat ribbon cable.PAGE: 72Hardware requirements for1 MHz expansion bus peripheralsNo power may be drawn from the BBC Microcomputer. Each peripheral shouldhave its own integral power supply, although a separate power unit may be used.Not more than one low-power Schottky TTL load may be presented to any bus lineby each peripheral.A 1 MHz Bus feed-through connector should be provided. Connection to the BBCMicrocomputer should be via 600mm of 34-way ribbon cable terminated with a 34-way IDC socket, and fitted with strain relief. Please note that copying theTeletext Adapter's layout is not possible, because this has been given thespecial status of the last box in the chain.Optional bus termination should be provided on all bus lines except NRST , NNMIand NIRQ. The recommended termination is a 2K2 resistor to +5V and a 2K2resistor to ground for each line.Further requirements for equipment to be approved by Acorn ComputersAddress space within page &FC must be allocated by the Research andDevelopment Department of Acorn Computers Ltd.The dimensions of any peripheral and its associated integral power suppliesshould allow it to be fitted into the BBC Microcomputer Expansion Box.When housed in the Expansion Box, the equipment should meet BS415 Class 1specifications for electrical safety.Further details of the requirements and procedures for gaining approval shouldbe obtained from Acorn. The information included here is for guidance only andis not intended to be a full specification for approval.PAGE: 73Derivation of valid Page signals1MHz peripherals are clocked by a 1 MHz 50070 duty cycle square wave (chosen toallow chips such as the 6522 to use their timing elements reliably). The MasterSeries 65C12 normally operates with a 2MHz clock, but with a slow-down circuitwhich has the effect of stretching the 'clock high' period immediatelyfollowing the detection of a valid 1 MHz peripheral address.There are two problems as a result of this. First addresses will change and maymomentarily become 1Me 6522control register.Depression of either of the shift keys, or the control key does not generatean interrupt.The power supply unit produces 5 volts at around 2 amps and -5 volts at around50mA for use on the main circuit board. Auxiliary power for accessories isavailable on an external connector.DETAILED CIRCUIT OPERATIONIn this section, certain parts of the circuit will be described.Pins 4, 5, 6, and 7 of the video processor (IC6) produce 1, 2, 4 and 8MHzclocks in phase. A D-type flip flop (half of IC34) divides the 2M Hz clocksignal in order to produce the system 1 MHz clock. A 2MHz signal of suitablephase is produced at the output of another D-type (half of IC30) and this isfurther clocked through the second D-type (half of IC30), and via an OR gateproducing the normal 2MHz clock input to the microprocessor. Requests for a 1MHz processor cycle from the address decoding are fed via an inverter (1/6thof IC33) to the D-type (half of IC30) which remembers that a 1 MHz cycle hasbeen requested.At the appropriate time, as governed by the 2M Hz clock, one of the 2MHz clockcycles is marked off by the D-type (half of IC34) and when this happens theD-type that remembered that a request had been made is cleared.A 6MHz clock signal is required for the Teletext character generator (IC32).This signal is produced by knocking a reset flip flop (two quarters of IC40)backwards and forwards from 8MHz and 4MHz clock signals. The resulting flipflop output is then itself inverted according to the state of the 2M Hz clocksignal by an exclusive OR gate (of IC38). Glitches on this output are removedby R119 and C48 toPAGE: 25produce the 6MHz clock signal at Pin B of IC37.The dynamic RAMs are constantly cycled by a row address strobe signal which isproduced by a D-type connected to the 8 and 4MHz clock signals (half of lC44).This RAS signal then drives all of the dynamic RAMs via R106. The dynamic RAMsare divided into two banks of 16 kilobytes, that is two banks of 8 RAMs. Thesebanks are input- or output-enabled by virtue of having their column addressstrobe available. In Model A computers with only one bank of RAM only CAS 1 isused. 32-kilobyte computers have a second bank of RAMs selected by a 74L551circuit (IC28) which controls the 74S139 (half of IC45) producing the CASsignals. The other half of 74S139 (half of IC45) is used to select between theprocessor and CRT address lines.The video processor uncommitted logic array takes data bytes from the RAM atthe rate of sixteen bits per microsecond and then serialises them according tothe display mode required. The bit streams for serialisation are then fedthrough a block of high speed palette RAM which relates the logical colourfrom the serialiser to the physical colour to be produced on the display. Thepalette drive is 16x4 bits with the four bits representing red, green and bluedrives, together with a flash bit. The data bus input to the video processoris also used to access the mode control register when the device is chipselected. In the Teletext display mode, RGB information is fed straight intothe video processor from the SAA5050 for the cursor control to be added.VDU throughput is much enhanced by the use of hardware scroll. A register inthe CRTC is used to store the start of screen address in the screen memory.Thus, in order to scroll the screen, it is only necessary to increment thisregister by the number of characters per line and then write to the memoryaddress where the last screen data was and where the new screen line data nowneeds to go.The number of address lines from the CRTC used to address the screen memoryhas to be sufficient to cater for the biggest screen, which is 20 kilobytes,therefore, sufficient addresses to satisfy 32 kilobytes of screen memory areused. By the hardware scrolling technique the picture rolls around in 32kilobytes. Forexample, with a scroll of eight kilobytes in a 20kilobyte screen, the originalstart of screen for the 20 kilobyte mode was &3000. After the eight kilobytescroll, theHz addresses while the 2MHz CPU clock is low, but whilethe 1 MHzE signal is high. This could give rise to a spurious pulse on the chipselect. Second, if the CPU deliberately addresses a 1 MHz peripheral during thetime that 1 MHzE is high, the device will be addressed immediately, and thenagain when 1 MHzE is next high: this is because the CPU clock will be held'high' by the stretching circuit until the next coincident falling edge of the1 MHz and 2MHz clocks. This double access is not usually a problem except whenreading from or writing to a location twice has some additional effect: anexample of this is an interrupt flag which is cleared by reading it.These effects mean that the 1 MHzE Bus cannot be used as a conventional'address valid' signal. However, addresses will always be valid on the risingedge of 1 MHzE. If the chip select lines are latched by 1 MHzE, the cleansignal CNGFC (or CNPGFD) will be generated.Address space allocationPage FCPage FC is reserved for peripherals with small memory requirements. Only oneperipheral will be allocated to each group of addresses. Further allocationsmust be agreed with the R & D department of Acorn Computers Ltd.Initial allocations are:FC00 to FC0F Test HardwareFC10 to FC13 TeletextFC14 to FC1 F PrestelFC20 to FC27 IEEE 488 InterfaceFC28 to FC2F Acorn Expansion: spareFC30 to FC3F Cambridge Ring InterfaceFC40 to FC47 Winchester Disc InterfaceFC48 to FC7F Acorn Expansion : spareFC80 to FC8F Test HardwarePAGE: 74FC90 to FCBF Acorn Expansion: spareFCC0 to FCFE User ApplicationsFCFF Paging RegisterPage FDPage FD is used in conjunction with the paging register to provide a 64Kaddress space, accessed one page at a time. Each BBC Expansion Box will have apaging register on the back plane, thus data will be latched simultaneously Onevery Expansion Box. Data latched into the paging register will provide thetop eight address bits to the Eurocard back plane. These top address bits arereferred to as the 'Extended Page Number'. Any peripheral designed to locatein page FD without using an expansion back plane must latch and decode thepaging address information.To make this facility as easy to use as possible, nPGFD (a hazard-free versionof the signal available from PL12) will be connected to the back plane pin 24b,'Not Valid Memory Address' , and also OR-ed with the top four extended pageaddress lines as a link selectable option to pin 31a 'BLKO'. (the other optionon this pin will be n PGFC).Extended pages &00 to &7F are reserved for Acorn use, pages &80 to &FF may befreely used by special applications. The paging register will be reset to &00on power-up and BREAK.Since the paging register is a write-only latch, location &00EE in the zeropage of the BBC machine address map has been allocated as a RAM image of theregister. Note that this location will remain in the l/O processor's memorymap if a second processor is fitted.The importance of this image is that it allows interrupt routines to changethe paging register and restore it again afterwards.It is vital to change location &00EE BEFORE changing the paging registeritself. If you don't, then an interrupt may occur before you change the RAMimage and this will restore the paging register to the old value of &EE.A suitable sequence isLDA # new valueSTA &EESTA &FCFFUser routines should save the contents of &EE before changing the pagingregister and restore both &EE and &FCFF to this value before returning from theinterrupt.PAGE: 75Drawing not reproducedTiming requirementsParameter Symbol Min. Max.Address Set-up time t as 300 1000(& R/W Set-up time)Address Hold Time tah 30(& R/W Hold Time)NPGFC & NPGFD Set-up Time tcs 250 1000NPGFC & NPGFD Hold Time tch 30Write Data Set-up Time t dsw 150Write Data Hold Time t dhw 50Read Data Set-up Time t dsr 200Read Data Hold Time t dhr 30Note: The above timings are based on only one peripheral attached to theExpansion Bus. Heavy loading may slow the rise and fall times of 1 MHzE w current start of screen address is &5000 with the end of the screenas viewed by the CRTC at &5000 plus 20 kilobytes, that is &A000.The address &A000 is not physically in the RAM and it is therefore necessary tomodify this address in order to move it to the original start of the screen.This is done by adding 12 kilobytes to get the required physical address. Inthis way, the physical memory addresses are kept within the required range.For the different screen modes we need to add different numbers as their startof screen addresses are different.PAGE: 26The following table shows this:-Modes Screen Size Start of Screen Address Number to be added0,1,2 20K &3000 12K3 16K &4000 16K4,5 10K &5000 (or &1800) 22K6 8K &6000 (or &2000) 24KThe number to be added to the start screen address in order to keep thehardware scrolling within the correct physical memory address range is definedby the control lines CO and C1 from 74LS5259 (IC32). This number is thencomputed with the result being added to the higher CRTC refresh address linesby the CTRC multiplexer (IC31 ).PAGE: 273 MEMORY ORGANISATIONOperation of the RAM and ROM is controlled by the Memory Controller integratedcircuit. The principal function of this device is to control the memory paging.Memory MapThe 65C12 can directly address 64K locations. As over 1/2 Mbyte may beresident, a paging scheme is implemented. &FFFF ROM &FF00 } I/O or ROM } MemoryMapped I/0 &FE00 } ROM &E000 ROM/RAM (Region b) &C000 ROM/Sideways RAM &9000 ROM/RAM &8000 ROM/RAM (Region a) &3000 RAM &0000 Machine Memory MapThe current memory map is dictated by the contents of the two latches. ROMSELect and ACCess CONtrol located at &FE30 and &FE34 respectively. Thecontents of these two latches are:- d7 d6 d5 d4 d3 d2 d1 d0(&FE30)RAM 0 0 0 PM3 PM2 PM1 PM0(&FE34)IRR TST IFJ ITU Y X E DThe contents of ROMSEL dictate the selection of memory which resides from&8000 to &BFFF.PAGE: 28The contents of ACCON principally dictate the activity of two regions ofmemory. (a) &3000 to &7FFF (b) &C000 to &DFFFRandom-Access MemoryRAM is functionally split up into two regions. The main region supports thelanguage workspaces, buffers etc. and provides the bit-mapped screen. Thesecond region provides four 16K 'Sideways' RAM segments. These are link-selected into ROM locations 4,5,6 and 7. They may be deselected, reinstatingthe ROM sockets in blocks of 32 Kbytes.Within the main 64 Kbyte region, the lower 32K is used within the &0000 to&7FFF region of the CPU memory map. The 64K of DRAM is distributed as follows:- ----------------------------- Bits in ACCON &FFFF &7FFF With E or X active &B000 &3000 t --------------------------------------------- &DFFF s WithRam Y active CPUAddress &9000 &C000 t ADDRESS -------------------------------------------- &888F s RAM active &8000 ------------------------------------------- &8000 t &0000 ------------------------------------------ &0000 Summary of RAM memory mapThe upper 32K is split up into three, self-contiguous regions. The largestportion of this is a 20Kbyte region designated LYNNE. This can be overlayed onthe region (a) of main memory.When bit D in ACCCON is set, the CRT controller will display the contents ofLYNNE. When bit D is cleared, the region (a) of main memory will be displayed.PAGE: 29When bit E in ACCCON is set, if the address range is &3000 to &7FFF the CPUwill read/write Lynne:1. Wait until end of cycle2. Was the last cycle an opcode fetch (sync=1) From &C000 to &DFFF in RAM?Yes - go to 3No go to 43. Is this Cycle an opcode fetch?Yes go to 4No go to 54. Access main memory. Go to 15. Write Lynne. Go to 1This system allows for the screen bit map to be removed from the main CPUmemory map of which it occupithpossible adverse effects on timings.PAGE: 76R-S flip-flop with gated input which allows 'clean select' to be set low onlyif 1 MHzE is low. An alternative circuit using transparent flip-flops isshown on the circuit diagram for the Expansion Box back plane (Drawing107,000,)PAGE: 7711 THE MACHINEOPERATING SYSTEMThis section explains how to extend the MOS facilities of the microcomputer,such as the VDU driver and the TUBE interface. It includes a full address map(which has indicators showing where the MASTER 128 and the MASTER EconetTerminal differ from the earlier BBC machines), the vector allocations (whichare given in full) and details on the use of vectors with interrupts and theTube. It may be helpful to refer to the chapter on the MOS in Part 1 of theReference Manual for additional information.Address spacemapThe address space map, which shows the address allocations and the areas ofmemory used by the computer, indicates to a programmer which areas of thememory are available for him to use. However , it does not show individualinput/output allocations as they have already been documented in Part 1 of theReference Manual.Although this section explains how to use areas of memory which are normallyreserved for specific purposes, Acorn does not condone the practice, as it maylead to software incompatibility when used on a machine other than the one onwhich it was written or if the configuration of the machine is changed.Page0&0000-&008F. current language workspace - some languages e.g. BASIC, allowother programs to use areas of free memory,&0090-&009F. ECONET private workspace - not available for any other use.&00A0-&00A7. Non-Maskable Interrupts (NMl) workspace - may be used onlyafter NMI has been claimed. The source of the NMI has a filingsystem number allocated to it (rather than a ROM number) and itmust be able to service the calls &0B and &0C (which indicatesthat it is either in the 'sideways' region &8000 to &BFFF, or that itcan intercept OSBYTE &8F). NMls should not change anylocations unless they are specifically allowed to or unless it istheir own workspace.PAGE: 79&00A8-&00AF MOS scratch space. It is not necessary for this space to bepreserved between MOS system calls and therefore may be usedby other programs during this time. However, it is notrecommended for general use because the integrity of the spacewill not be preserved across MOS calls.&00B0-&00BF filing system scratch space - like the MOS scratch space it is notpreserved between system calls. During this time other programsmay use it although this practice is not recommended becausethey will not be preserved across filing system calls. 'Hidden'filing system calls e.g. those produced by OSWRCH if thecommand *SPOOL has been used also use this space.&00C0-&00CF current filing system workspace - under no circumstances mustthis area be used because it may be corrupted at any time&00D0-&00FF MOS workspace - not available for use by other programs. TheVDU driver is fully explained in section E of Part 1 of theReference Manual,In previous BBC microcomputers this area contained variouspointers and flags for 1/O operations. This is not the case with theMaster Series.Pages 1 to &D&0100-&01FF processor stack and error messages buffer. The stack followsnormal 6502 practice and works as a LIFO buffer at the top of thepage. Error messages are stored temporarily at the bottom of thepage.&0200-&0235: vector addresses. For more details of this area please refer tothe section on Extending the MOS.&0236-&028F. main MOS variables - not recommended for any other purpose.&0290-&02FF . MOS workspace - not available for other purposes.&0300-&037F. VDU variables. It is only possible to us this area for graphicsroutines, more details on the use of these are available insections D, E and F of the Reference Manual Part 1 . In earlierBBC microcomputers some of the variables had differentfunctions, details of which are given in the Appendices.PAGE: 80&0380-&03DF Cassette Fies a significant proportion. It will, however,only work if the screen is being accessed by opcodes from a known region -i.e. the MOS VDU drivers.A mechanism is also provided to permit 'illegal' screen access. Bit X inACCCON, when set, causes all accesses to region (a) to be re-directed to LYNNE.This occurs irrespective of the opcode address, hence considerable care must beexercised in its use. When cleared the memory map returns to its usual format.In the same way that the BASIC variable HIMEM will always have the value &8000when LYNNE is used, it is desirable for the variable PAGE to have the value&E00, irrespective of the current filing system. This is achieved by providinga filing system workspace. Bit Y in ACCCON when set, causes 8Kbyte of RAM,referred to as HAZEL, to be overlayed on the MOS VDU drivers, i.e. from &C000to &DFFF. When this bit has been set, no calls may be made to the MOS for VDUoperation. The code which performs this paging operation is responsible forresetting the Y bit, as no hardware is provided for this purpose.The remaining bits in ACCCON are used to control various peripheral systems.ITU, when set, enables the CPU to access the internal second processorrather than the external one.IRR is InterRupt Request. When set, this bit causes an open drain output topull the CPU NlRQ pin down to Vss.PAGE: 30ROMSELThe contents of ROMSEL determine the paging of memory in the 16K region &8000to &BFFF. One of sixteen 16Kbyte ROM memory segments may be selected. Oneadditional 4Kbyte RAM segment may be selected from &8000 to &8FFF.Eight of the segments are assumed to be in four 32Kbyte ROMs where the leastsignificant bit of ROMSEL selects between the upper and lower segments. Sevenof the segments exist together with a ROM which is active from &C000 to &FFFFwithin a 128Kbyte ROM. This ROM is connected via a separate data bus. The four32Kbyte devices and one 16Kbyte device are connected in a matrixing scheme. Segments 8 7,6 5,4 Chip Selects o o o or RAM enablingOutput o-----------------------------------EnableCartridge o----------------------------------ROMsChip Select o o Segments 3,2 1,0In this way, fewer connections to the controller logic are required to selecta given ROM, although the power dissipation will be increased if all the ROMsin one column are inserted. A chip select will be driven low if an access toone of the segments (4 to 8) is required. If a cartridge ROM is required, thenthe Cartridge ROM chip select will be driven high. All chip selects are adecode of the CPU address most significant nibble. An output enable is turnedactive low during the CPU d2 period depending on which segment is required.The segment to be selected is determined by the binary number held within theleast significant nibble of ROMSEL.Overlaid RAM in ROM areaWhen the bit RAM is set in ROMSEL, accesses to the region &8000 to &8FFF areredirected from the currently selected ROM to a region of RAM referred to asANDY. It is the responsibility of the code which set RAM to clear it afteraccessing ANDY. This is necessary to ensure correct operation of software inROM.A further 64 Kbyte of RAM is available as four pages of 16 Kbyte from &8000 to&BFFF. The ROM slots 4,5,6 and 7 are not active when this RAM is link-selectedto be active.PAGE: 31Drawing not reproducedDRAM timingRAS is generated from 4M and 8M by the D-type IC28 pin 9. CAS for the mainDRAMs is generated from 2M, inverted by a NAND in IC34 to give phi2 IN, gatedwith DRAMEN which enables the main RAM, and finally gated with 4M throughanother NAND in IC34.PAGE: 324 SLOW DATA BUSSeveral internal components need to work with access cycles slower than theCPU's normal 1 or 2 MHz rates. These are: 1 ) Keyboard 2) Sound Generator 3) Real Time Clock/RAMDirect access of these devices is not recommended, as their operation may besubtly related to other functions, or be time-critical, or could causemalfunction if not peiling System workspace - available only if the CFS isnot used.&03E0-&03FF keyboard input buffer - available only if the keyboard buffer hasbeen replaced.&0400-&07FFlanguage workspace - may be used if the current languageallows (e.g. BASIC ). It is also used for the relocation of the hostcommunications routines with second processors.&0800-&087F sound workspace - its use is not recommended as this maycause the generation of spurious sounds.&0880-&08BF printer buffer - may be used for other purposes if printing is notrequired.&08C0-&08FF workspace for the sound envelopes 1 to 4 - available for otherpurposes if the envelopes are not used.&0900-&09BF RS423 output buffer, cassette output buffer for access to the firstpart of sequential files or workspace for sound envelopes 5 to 16- otherwise available for other purposes.&09C0-&09FF Speech buffer or cassette output buffer for access to the secondpart of sequential files - available to users if not required for thesepurposes.&0A00-&0AFF RS423 input buffer or the cassette input buffer for access tosequential files - available for other uses if not required for thesepurposes.&0B00-&0CFF. ECONET workspace - may not be used for any other purpose ifat any time the computer will be connected to an ECONETsystem. In previous BBC microcomputers this area was used forthe soft key buffer and the upper 32 characters of the explodedfont. This means that previous routines for writing a soft keydefinition directly into the memory can no longer be used.Correct operation on the Master Series and on the earlier BBCmachines can be achieved by using the OSCLI interlace.&0D00-&0D5F. NMI routine workspace. In order to make use of this area forother uses NMls must be claimed (paged ROM service call&0C) . The same restrictions apply to the use of this area as to&00A0-&00A7 which is described above. On earlier BBCmicrocomputers this region extended to &0D9E.PAGE: 81&0D60-&0D7F ECONET workspace - it may be used for other purposes if themachine is not going to be connected to an ECONET system.&0D80-&0D91 : available for user programs.&0D92-&0D9E: Reserved for a Trackerball or Mouse. It is necessary for thesedevices to have immediate access to non-paged memory in orderto service the interrupts from their reference phase signals. Thisarea has been reserved for fast updating of their counters.&0D9F-&0DEF extended vector address set, more details of which can be foundin the section on extending the MOS.&0DF0-&0DFF paged ROM workspace. Usually one byte for each ROM is usedfor the high byte of the private workspace address. Some ROMs,such as the DNFS also use it to indicate that they are not activeby resetting bit 7. The reason for the inactivity may be, forexample, that essential hardware is not present or that aparticular filing system is dormant.Pages &E to &7FThe allocation of this area of the memory is variable. Some of the pages at thelower addresses may be used by the paged ROMs or by programs that raise theOperating System High Water Mark (OSHWM). Some pages at the higheraddresses may be allocated to the screen, if it is not in shadow mode. Theremaining memory is allocated to user memory, i.e. language workspace.In the Master Series soft character definitions are held in RAM at &8000,whereas earlier BBC microcomputers stored them in RAM above &0E00, raisingOSHWM.Pages &80 to &BFAt any one time, one of sixteen images resides in the memory pages &80 to &BF.These images may be in ROM, RAM, or EPROM and include parts of the operatingsystem, the sideways MOS ROM (ROM &F and the top 1.5k of the ROM &E).The MOS makes the paged ROM code in the address range &8000 to &8FFFunavailable during graphics and soft-key calls by setting the high bit of theROMselect latch high. This swaps in 4k from a further 32k of RAM. Paged ROMS whichneed to use of this area can do so by calling routines given in the VDU driversspecification section of Part 1 of the Reference Manual. Note great care mustbetaken when laying out these ROMS trformed correctly. The same functions may be provided bycompletely different hardware in earlier or subsequent products. For those whoneed direct access, rather than using the MOS, it is advisable to disable.interrupts whilst accessing any of these devices because the MOS may changesome of the settings whilst servicing an interrupt from another source.Memory LocationsAll these devices are accessed through the System VIA located at &FE40-9. TheSlow Data Bus is connected to the 8-bit A port at &FE41. This is referred toas PA[0:7]. The B port at &FE40 is the control bus.Slow Data Control Port (&FE40)Writing the following values will have the indicated effect:PA[7] DXXX XXXX - RTC/RAM Address strobe : Active highPA[6] XDXX XXXX - RTC/RAM Chip select : Active lowPA[7] XXXX D111 - Shift lock : Active lowPA[7] XXXX D110 -Capslock: : Active lowPA[0:3] XXXX D101 - Hardware Scroll 1 (HSI)PA[0:3] XXXX D100 - Hardware Scroll 0 (HS0)PA[0:3] XXXX D011 - Keyboard Enable (KBEN)PA[0:3] XXXX D010 - RTC/RAM Data Strobe : Active highPA[0:3] XXXX D001 - RTC/RAM Read Write : High for ReadPA[0:3] XXXX D000 - Sound Generator write : Active lowD is set high or low as needed.The hardware scroll bits HS[0:1] are used in VDU control.PAGE: 33KeyboardThe keyboard is accessed as a matrix of 8 rows by 13 columns. To access anyparticular key, it is necessary to assert KBEN and set the column and rowaddresses of that key on port A thus:PA[3:0] (outputs) are the column addressPA[6:4] (outputs) are the row addressPA[7] (input) is the key output - active low if pressed.An interrupt will be caused by CA2 via R13[0] (bit 0 of &FE4D) whenever a keyis pressed.Sound GeneratorWithin the MASTER 128, the sound generator chip is write-only. The write strobemust be asserted low for the data PA[0:7] to be written into it. Data must bestable during the 8ms in which the write strobe must be low.Real-time clock/CMOS RAMFifty bytes of battery-backed CMOS RAM are available within the real-time clockchip. Twenty bytes are used to store the system configuration, ten arereserved for future use by Acorn, ten are reserved for used by third-partymanufacturers and ten are available for used by the user. Extreme care shouldbe taken in the direct control of this device to ensure integrity of thecomputer's configuration status. The MOS should be used for the normalreading/writing of the RAM. FX calls 162 and 163 (OSBYTES &A2,&A3) are used toaccess the RAM. OSWORDs &14 and &15 should be used to read/write the time.CMOS RAM AllocationAddress (offset) Function0 Station Number1 File server station number2 File server bridge number3 Printer server station number4 Printer server bridge number5 Default filing system/language6-7 ROM frugal bits (set/cleared by *INSERT/*UNPLUG)8 EDIT start-up settings9 reserved for telecommunications applications10 VDU Mode and *TV settingsPAGE: 3411 ADFS start-up options and floppy drive parameters12 Keyboard auto-repeat delay13 Keyboard auto-repeat rate14 Printer ignore character15 Default printer type, serial baud rate, ignore status and TUBE select16 Default serial data format, auto boot option, internal/external TUBE use, BELL amplitude17 ANFS configuration control (on hard reset) bit 0 : Claim two static pages at &0E00 bit 1 : Findlib bootstrap option bit 2 : Reserved bit 3 : User/Application bit 4 : User/Application bit 5 : Reserved for ANFS protection mechanisms bit 6 : Display version messages18-1920-29 Reserved for future use by Acorn30-45 For ROMs 0-15 (one per ROM)46-49 Available for user applicationsNote that the station number cannot be written to, and has to be accessed bycode similar to that listed in the RTC alarm section.Real Time Alarm FunctionsThe MOS does not provide control of the device's alarm facilities as these areonly available on a daily basis, i.e. the alarm cannot be programmed tooperate on a specific dato avoid attempts to execute ROM code withinthe overlaid area.PAGE: 82Sideways ROM numbers 0,1,2 and 3 are allocated to the cartridges and a further'vertical' paging mechanism may be used with these. When using the 'vertical'paging mechanism some 1Mbit and 512kbit EPROMS are arranged as sixteen andeight pages of 16k bits respectively. When these devices are plugged into thecartridge slots they will appear as a 16k byte image, but any one of theremaining seven (for the 1 Mbit) or three (for the 512kbit) images may beobtained by writing to the EPROM with the vertical page number. This a majordeparture from standard EPROMS and allows 512k bytes to be fitted into fourEPROMS and yet only use 16k of the computer's address space. This isillustrated below.To insert the paged EPROM into the memory map of the computer the value of theEPROM is written to address &FE30. The required vertical image is then selectedby writing to any location in the range &8000 to &BFFF. Note this selection ismaintained even if through a hard break (e.g. CTRL-BREAK). The next access tothese sideways EPROMS will be from the new image. On power-up the specialEPROMS default to vertical page 0. To use this facility include a standard ROMheader line for each vertical page. An example of a typical paged EPROM is the27513, which is four pages of 16k bytes.PAGE: 83Pages &C0 to &DF and page &FFThe main MOS ROM resides in the areas &C0 to &DF and &FF However, in thestandard configuration pages &C0 to &DF of the MOS are not directly readable,because the filing system RAM is switched into this area. This part of the MOScontains the graphics routines and is enabled when needed. Another featurewhich should be noted is that access by instructions in the area &C0 to &DF todata in the locations &3000 to &7FFF are automatically mapped into either themain memory or the 'shadow' screen memory depending on the current screen mode.The state of the memory map is determined by the ROM select latch at &FE30 andthe memory access latch at &FE34. If these registers have been changed, thenthe memory map may not behave as described above.Page&FCPage &FC is mapped to either the external 1 MHz Bus or the cartridges via thesignal INFC (INternal FC). The cartridges will be accessed when bit IFJ is setin the register at &FE34. This page is intended to be used for memory mappedhardware.Page &FDThis page is also mapped to the external 1 MHz Bus or the cartridges by thesignal INFD. This page will access the cartridges when the IFJ bit of theregister &FE34 is set. The page &FD is intended to be used for accessing theremote memory. Note that location &FCFF is reserved as a paging register toallow up to 64k bytes to be accessed through this page.The Second 32k of RAM.The second 32k of RAM does not occupy one contiguous block of addresses, but isallocated as follows:-&3000-&7FFF shadow screen memory - any part of it not required by the currentscreen mode is available for user programs. Access is gained bymanipulating the memory map latch. However, note that thecommand *MOVE will use this area if one of the non-shadowmodes or a shadow mode occupying less than 20k bytes, isbeing used.&8000-&83FF soft-key expansion buffer - not available for any other purpose.PAGE: 84&8400-&88FF VDU workspace which can only be used for VDU routines thatrequire large amounts of workspace, e.g. flood filling. Care mustbe taken to avoid conflicts between different routines of this sort.Commercial software should avoid using these areas.&8900-&8FFF character definitions.&C000-&DBFF paged ROM workspace. The ROMS use service calls to claimthe area. This is a similar procedure to the one used to claimspace above &E00. Static workspace in this area or above &E00should only be used by filing systems although any ROM mayhave private workspace.&DC00-&DCFF MOS CLI buffer - this area is corrupted by all * commands, andits use for other programs is therefore not recommended.&DD00-&DEFF transient utility workspace and it is available foe. The alarm operates by generating an interrupt whenthe real time counters are equal to the alarm time registers.The connection of the clock chip to the system interrupt line is via ashorting bar on Link4. This would have to be fitted by the user. For the userwilling to reserve some of the other battery-backed RAM for the target date,the following routine should be used to access the alarm and control registers.It is similar to those within the MOS and obeys the rules for reliableoperation. It is in the style of BBC BASIC assembler.pbq=&FE40 :REM Port Bpaq&FE41 :REM Port Addraq=&FE43 :REM Port B data direction register : REM 1 = Output : REM 0 = InputPAGE: 35EQUB &02 :EQUB pbq DS activeEQUB &82:EQUB pbq Address strobe inactiveEQUB &FF:EQUB ddraq OutputsEQUB &0E :EQUB paq slow bus address (see note 1)EQUB &C2:EQUB pbq chip select activeEQUB &42:EQUB pbq Latch addressEQUB &41:EQUB pbq Select write modeEQUB &FF:EQUB ddraq OutputsEQUB &4A: EQUB pbq Data strobe activeEQUB &00:EQUB paq Write the data (see note 2)EQUB &42:EQUB pbq Data strobe inactiveEQUB &02:EQUB pbq Chip select inactiveEQUB &00:EQUB ddraq Inputs again Note 1 This address should be made variable as it will be necessary to access one of a number of registers. Note 2 Separate sequences may be necessary for read and write operations, depending on personal preferences.RTC RAM Access RestrictionsThe real-time clock section of the chip is updated from the real-time countersonce every second. It is important that the user program does not try to accessthem at the same time as this will give erroneous results. There are threeways that the chip gives notice that it is in the process of updating theregisters. These are documented in the manufacturers data sheet. Wherepossible it is recommended that an alternative approach be used which ensuresuser access. This is to set the SET (bit 7) flag in Register &B (the controlregister). It prevents the chip from updating the registers but does not affectthe counted time. When the SET bit is reset, the registers will be reset to thecurrent time approximately within the next second. Avoidance of this criticalregion, or the overriding of it, must be done whenever the real time or alarmregisters are written.The code should be assembled to operate in sideways RAM (i.e. in the region&8000 to &BFFF). The program is essentially in two parts:a) To set the alarm time, an OSCLI command which will not conflict with anyother in the machine, e.g. *SETALARM hh:mm:ss should be devised. This involvesrecognising Service Call &04 (Offer Command). The program should interpretthe given time string as appropriate and load it into the alarm registers thenre- enable the counter-register transfers and finally enable the alarminterrupt by setting the AI E (bit 5) flag in Register &B.PAGE: 36b) To respond to the alarm, the code should respond to Service Call &05(Unknown Interrupt). The alarm flag - AF (bit 5) in Register &C should beexamined to ascertain whether the alarm has occurred or not. If so, theappropriate action should be taken and the call should be claimed, otherwisethe call should not be claimed. The interrupt will be cleared by readingregister &C.PAGE: 37 5 KEYBOARD CONTROLLERKeyboard OperationDuring free run mode, the keyboard column lines are continually scanned byincrementing a counter, decoding its outputs and pulling low a column line.Any key depressed will cause the interrupt to be generated. A signal, KeyBoardENable is generated to stop free running mode. The counter contents are thenloaded by CPU operation to determine on which row the key was pressed. The rowsare then individually selected to determine which key was pressed. KBDENC issupplied with data from the slow data bus:-PA0 to PA6 (slow bus connections):- PA0 to PA3 are the column select inputsand PA4 to PA6 are the row select inputs. PA7 is a three-state connectionwhich ir user written* commands and the *MOVE command.&DF00-&DFFF. MOS workspace only. It may not be used for any otherprograms.VDU Workspace&00D0-&00D9: non-transient VDU variables and should not be used by any otherprogram.&00DA-&00E1 : VDU scratch space and not available for other purposes.&0300-&037F VDU workspace. There are two forms of graphics co-ordinate,internal and external. The external graphics co-ordinate is theone used by the BASIC PLOT command. The internal graphicsco-ordinate is derived from the external by taking into account thegraphics origin and scaling so that it is measured in pixels, bothhorizontally and vertically. Graphics co-ordinates are stored infour bytes, with the low byte of the X co-ordinate first.&8400-&87FF VDU workspace in the shadow RAM used as scratch space forflood filling. If the flood fill is active, one of the values0, 1 ,2,3,4,5,6,7,8,9 or A will appear in the location &8601.Therefore any routines that need to use this space must haveone or more values allocated to them by Acorn Services andTraining Department. If a routine in the set changes any byte inthe VDU workspace, it must leave one of its values in the locationPAGE: 85&8601. If the workspace is assumed to contain any valid data, itmust check that location &8601 contains a suitable value. Iflocation &8601 does not contain a valid value then the routinemust take the appropriate action.VDU workspace allocations&0000-&000F scratch space e.g. flood fill.&001 0-&000F not allocated.&8800-&882F non-transient VDU variables.&8830-&88BF VDU scratch space.&88C0-&88FF reserved for future use by non-transient VDU variables.&8900-&8FFF current character definitions.Earlier BBC Microcomputers and the Acorn Electron&00D0-&00D9 VDU variables. These are not transient and should only bealtered in keeping with their function.&00DA-&00DF VDU scratch space - it does not need to be preserved betweenVDU calls, and is not preserved across them.&00E0-&00E1 non-transient VDU variables.&0300-&0327 non-transient VDU variables.&0328-&0349 With the exception of &338, which when in teletext mode is anon-transient variable, this area is a VDU scratch space.&034A-&037F non-transient variables.Extending the MOSThere are occasions when the standard MOS facilities do not meet therequirements of a particular application e.g. when additional hardware has beenincluded in the system. For such situations it is possible to extend or insome cases replace most of the MOS functions with user defined ones. It ispossible to make extensions to both the time-dependent and the time-independentfunctions. It is recommended that users become familiar with thetime-independent functions before changing the time-dependent functions whichare more complex.Time-lndependent FunctionsTime-independent functions may be invoked at any time. The main MOS functionsare entered by calling a subroutine (JSR) at the appropriate entry point. (Forexample, OSWORD is entered at &FFF1 .) The actual entry point for the start ofthe function is stored in a vector table. The routine is accessed by anindirect Jump (JMP) command located at the entry point. In the previousexample of OSWORD,PAGE: 86the vector address is &20C and the MOS code at the OSWORD entry point is JMP(&20C). The vectors are stored as a lookup table in RAM at addresses &200-235.The table is initialised on RESET and by substituting vectors which point touser-supplied code it is possible to change the MOS functions.Vectors in co-processorsMost of the MOS calls are available in the operating system of a co-processor.However, it should be borne in mind that although re-directing a vector in theco-processor will only affect the co-processor, re-directing a vector in thehost will affect both the co-processor and the host. For example, interceptingthe OSWRCH command with WRCHV in the host in order to change all lower casecharacters to upper case will change all the output from the host and theco-processor. However, if the intercept takes place in the co-s driven active low when a row/column combination describes a depressedkey.PA7 (row data bit output):- This 3-state output provides the ROW data signal tothe host system. It is enabled by the nKBEN signal and its output is high ifthe row address set up on PA4-PA6 points to a row which is at logic low.R0 to R7:- The keyboard row input connections are normally held high byinternal pull-up resistors. If a key is depressed it will cause theappropriate row connection to be pulled low when its column is selected.C0 to C14:- These open collector column driving outputs are sequentially takenactive low in auto scan mode at a rate of 1 MHz. In polled mode (nKBEN activelow), the slow bus inputs PA0 to PA3 determine which output will be low. Theselected column output is a direct decode of these inputs.CA2:- Connected to the system VIA, this output will cause the VIA to generatean n IRQ. The line will be active low when an active key is detected.nKBEN:- Generated by the system VIA, this line is taken active low to enablethe row and column addresses to be determined by the Operating System.MHz1:- Timing reference for the positive edge triggered counter and the resetgenerator circuit.SWTI (switch input):- A transition from 5v to 0v or 0v to 5v on this inputwill cause an active low pulse of 200ms to be generated on pin22 (RSTO).PAGE: 38RSTO (reset output):- This open-drain output is triggered by a transition onthe Switch Input pin SWTI and provides a logic low output pulse of at least200mS. For example if SWTI is taken from 0v to 5v via a mechanical switch, theoutput will immediately fall to 0v, hold low for 200mS after switch bounce andthen rise to 5V again.VCCI VCC2 (positive supply):- These pins must both be connected to the positivepole of a suitable power supply.GNDl, GND2 (ground):- These pins must both be connected to the power supplyGND or RETURN line.1 R0 VCCI 402 R6 MHZl 393 R7 NKBEN 384 R2 PA4 375 R1 PA5 366 C11 PA6 357 C10 PAO 348 C12 PAl 339 C0 PA2 3210 GND2 PA3 3111 C2 VCC2 3012 C9 PA7 2913 C4 CA2 2814 C5 R5 2715 C6 R4 2616 C8 R3 2517 C7 C13 2418 C3 C14 2319 C1 RST0 2220 GND1 SWT1 21KBDENC connectionsThe keyboard encoder scans the keyboard matrix, interrupting the CPU when a keyis pressed. The MOS then puts the device in manual mode and scans the columnsuntil it finds one where a key has been pressed. It then scans the rows untilit finds one where a key has been pressed. It then goes on to check othercolumns and rows to find out if any other keys have been pressed. Thiscontinues at 10ms intervals (under the control of the system timer) until nokeys are pressed, at which point the MOS switches the device back to automaticscanning. The operation of this circuit can be split into three modes.PAGE: 39Mode 1 - Free runThis is the state assumed during normal operating periods with no key pressed.The keyboard is constantly scanned, with no intervention from the CPU, until akey is pressed. A four-bit counter, clocked by a 1 MHz signal drives afour-to-fifteen line decoder. This causes a logic low to ripple through C0 toC14. Should any key be pressed, the column in question will be connected tothe relevant row, which will pull one of the inputs to the 7NAND gate low. Asthe other six inputs are all pulled high, the NAND output will go high andthus generate an interrupt signal on pin CA2.Mode 2 - Column detectionThe interrupt signal is registered in the host system which then takes acloser look at the keyboard. The Operating System keyboard scan routine isentered and individual addresses may be set up on PA0 to PA3. These aresynchronously loaded into the counter while nKBEN is low, thus causing eachkeyboard column to be individually scanned. The interrupt CA2 may be examined after each counterload to see if the correct column has been reached. If this is so then thecolumn address is held on the counter and stored for future reference, if notthen the next processor thenonly the output from the current application will be changed, anything fromthe filing systems which operate only in the host will remain unchanged.Vectors In Sideways ROM/RAMExtended vectors may be used to point to sideways memory rather than a locationin non-paged memory. This allows the user to specify the ROM (or RAM) slotnumber as well as the target address. The procedure is shown below.a) Using OSBYTE 168 , read the start of the extended vectorspace ().b) Starting at ( + 3*), place the following data intomemory.().< entry point in ROM (most significant byte)>.< ROM slot number >.c) the relevant vector is then changed to.&FF00 + (-&0200)*3/2The vector's location () is selected from the table shown below. Thenumber (-&0200)/2 is called the vector number.PAGE: 87MOS Function Vector TableFunction Entry Point Vector Name Vector LocationMain MOS FunctionsOSBYTE &FFF4 BYTEV &20AOSWORD &FFF1 WORDV &20COSCLI &FFF7 CLIV &208OSRDCH &FFE0 RDCHV &210OSWRCH &FFEE WRCHV &20EOSEVEN Via Vector EVENTV &220Error (BRK) vector BRKV &202User vector USERV &200Input controlkeyboard operation KEYV &228Output Controlunknown plot codes VDUV &226user print vector UPTV &222Buffer controlbuffer insert vector INSV &22Abuffer remove vector REMV &22Cbuffer controI CNPV &22EFiling system functionsOSFIND &FFCE FINDV &21COSGPBP &FFD1 GPBPV &21AOSGBPUT &FFD4 BPUTV &218OSBGET &FFD7 BGETV &216OSARGS &FFDA ARGSV &214OSFILE &FFDD FILEV &212Filing system control FSCV &21EECONET vector NETV &224Spare (indirect) vectors IND1V &230 IND2V &232 IND3V &234Interrupt request vectorshigh priority devices IRQ1V &204low priority devices IRQ2V &206Notes1) OSRDSC, OSWRSC, OSNEWL, OSASCI, GSINIT and GSREAD are notvectored because they have very specific functions, details of which are in theReference Manuals Parts 1 and 2.PAGE: 882) It is only possible to access functions without entry points by usingvectors. User code must call the function indirectly by JMP (),rather than directly by JMP ,3) OSEVEN has been included in this section because although it is often usedas a means of simulating real-time events its use is not restricted to this.4) USERV has been included in the MOS sub-section because it is used to passthe unknown OSWORDS &E0 to &FF the user.5) The time-dependent functions use the RQ vectors and are included here forcompleteness.Entry pointed vectorsThe entry pointed vectors are used for most of the MOS routines. Part 1 of theReference Manual fully describes the entry and exit conditions.Vectors without MOS entry pointsThese are mainly user defined which means that MOS entry points cannot bedefined.EVENTVSystem events may be simulated by using OSEVEN. OSEVEN is called with Xbeing the event to which the routine is to be passed. A and Y are thentransposed and X is preserved The user's routine must preserve all theregisters when passed on through EVENTV.On entry Y corresponds to the event. The following table lists the values forY and their corresponding events. The values for X and Y are event specific.Event 0 - output buffer emptyX - buffer number Y-unused.0 keyboard1 RS423 input2 RS423 output3 printer4 sound channel 05 sound channel 16 sound channel 27 sound channel 38 speechPAGE: 89Event 1 - input buffer fullX - buffer number(as event 0) Y - overflow characterEvent 2 - character entering bufferX-unused Y - most-recent characterEvent 3 - ADC conversion completeX-unused Y - ADC channel measuredEvent 4 - start of vertical sync. (retrace)X-unused Y-unusedindicates a retrace has startedEvent 5 - interval timer crossing zeroX - unused Y-unusedsystem VIA interval decremented to zeroEvent 6 - ESaddress is loaded into the counter.Mode 3 - Row detectionHaving discovered and held the column address, the host may now set upaddresses on PA4 to PA6. These are fed to an eight-way data selector and causeone of the eight rows to become available on the W output in an inverted state. Should the correct row be found, W will go high and the current address willbe stored.PAGE: 40Keyboard MatrixThe keys are physically arranged as a QWERTY type keyboard with ten functionkeys, four cursor control keys and a nineteen-key numeric keypad. C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12R0 ESC f1 f2 f3 f5 f6 f8 f9 A @ 4 5 2R1 TAB Z sp V B M , <. >/ ?cpy 0 1 3R2 SHIFT LOCK S C G H N L +; (] del # * ,R3 CAPS LOCK A X F Y J K @ *: ret / del .R4 1! "2 D R &6 U O P )[ @ + retR5 f0 W E T 7' I )9 0 / @ 8 9 R6 Q #3 $4 %5 `4 (8 `7 =- @ 6 7 R7 SHIFT CTL INKEY NUMBERSkey Inkey Number key Inkey Numberf0 -33 4 -19f1 -114 5 -20f2 -115 6 -53f3 -116 7 -37f4 -21 8 -22f5 -117 9 -39f6 -118 , -103f7 -32 _ -24f8 -119 . -104f9 -120 / -105PAGE: 41key INKEY number key INKEY numberA -66 [ -57B -101 \ -121C -83 ] -89D -51 ^ -25E -35 - -41F -68 : -73G -84 ; -88H -85 @ -72J -70 ESCAPE -113K -71 TAB -97L -87 CAPS LOCK -65M -102 SHIFT LOCK -81N -86 CTRL -2O -55 SHIFT -1P -56 SPACE -99Q -17 DELETE -90R -52 RETURN -74S -82 COPY -106T -36 ­ -58U -54 ® -26V -100 -122W -34 ¯ -42X -67 keypad 0 -107Y -69 keypad 1 -108Z -98 keypad 2 -1250 -40 keypad 3 -1091 -49 keypad 4 -1232 -50 keypad 5 -1243 -18 keypad 6 -27keypad / -75 keypad 7 -28keypad £ -91 keypad 8 -43keypad * -92 keypad 9 -44keypad, -93 keypad + -59keypad RETURN -61 keypad - -60keypad DELETE -76PAGE: 426 SCREEN DISPLAYScreen OutputThree chips are primarily responsible for providing the screen output:-a) Acorn VIDPROC ULA chipb) 6845 cathode ray tube controllerc) Acorn CHROMA MSI video matrixing chipThe video processor takes a byte-wide data stream from memory, serialises itaccording to the screen mode in use, passes it through a palette to providelogical to physical colour transformation and on to the RGB outputs. From herethe video data is buffered for connection to an RGB monitor and mixed for usewith the composite video and colour television outputs.High Resolution ModesThe 6845 generates a linear memory address sequence which increments every0.5ms or 1 ms, depending on the video bandwidth selected and video data format.The amount of memory reserved for screen use is also varied. The availableoptions areVideo Data Formats'Mode' Format Reserved Memory Pixels/Byte Bytes 0 8 20K 1 4 20K 2 2 20K 3 8 16K 4 8 10K 5 4 10K 6 8 8K 7 Teletext 1K 128 8 20K ] 129 4 20K ] 130 2 20K ] Reserved 131 8 20K ] in 132 8 20K ] LYNNE 133 4 20K ] 134 8 20K ] 135 Teletext 20K ]PAGE: 43All modes except 7 and 135 display a bit-mapped image of the reserved memory.The 6845 may be re-programmed to display any arbitrary section of memory. Ifthis is done, however, the hardware scrolling will not work correctly, as itassumes that the screen memory is in its usual location. The screen alwaysends at &7FFF and starts 1,8,1 0 or 20K below, depending CAPE has been pressedX-unused Y - unusedEscape condition will not be generated or transmitted to parasiteEvent 7 - RS423 errorX - 6850 status Y - char received shifted rightEvent 8 - network event X-lsb Y - msb of remotely requested procedureEvent9 - user eventconditions are user-definedEvent &FE - network receiveThis event is enabled by *FX52,150 ctrl blck # and disabled by *FX52,100. It isnot affected by *FX13 and *FX14.Note an escape condition will not be transmitted to the parasite when theESCAPE key is pressed if an escape condition has not been generated bychanging bits 6 and 7 in location &00FF.BRK instructionThe instruction BRK is the software equivalent of the 65C12 processor to ahardware Interrupt ReQuest (IRQ). BRK fetches the next instruction from theaddress stored in &FFFE and &FFFF, which is the address of the IRQ routine inthe MOS. The I RQ routine sets up the stack as described below and then viaBRKV performs a JMP.PAGE: 90The BBC microcomputers use this mechanism to indicate an unrecoverablesoftware fault and use the vector to implement error routines. For example,languages use the vector to point to their error handlers. The user routinespointed to by the BRKV command should exit via the old contents of the vectorbecause the stack will have been modified.The command ReTurn from Interrupt (RTI) should not be used as it may cause theprogram to jump into the stack where the error message might be.On entry A, X, and Y will remain set up as they were before the BRK command.An RTI instruction will be set to return the stack pointer to the location twobytes after the BRK command. RTI should only be used if special user code hasbeen sent after the BRK instruction as opposed to the error structure describednext.The locations &00FD and &00FE are a pointer, placed by the MOS, to the locationafter the BRK.The current stack pointer will be contained in location &00F0.The slot number of the ROM that was active when the BRK instruction was issuedcan be read by OSBYTE &6A.The following structure should be placed after the BRK. BRK < first byte of error message> ' ' ' < last byte of error message > &00The null is a recognised means of ending a message. The handler shouldinterpretit accordingly.BRK instruction in single processor systemsThe Entry Structure is set up as shown above, but Service Call 6 (BRK) isperformed before the vector indirection is performed so that the filingsystems, or any other service ROM, can take the appropriate action.PAGE: 91BRK instruction in co-processor systemsIf the BRK is executed in the host, the above structure is set up in theco-processor but terminated with an 1 RQ. This causes the Tube OperatingSystem (TOS) to make a copy of the BRK and error string in its own memory. TheBRK is then executed; it is treated as if the BRK had originated in theco-processor. If the BRK is originally executed in the co-processor, the errorpointer is calculated as normal, interrupts are re-enabled and BRKV is used.Service Call 6 is not issued.USERVThe USERV instructions cause program flow to be directed via USERV. This maybe used for user-defined OSWORD calls. Entry to routines via the *CODE and*LINE commands is simplified by using the USERV vector.EntryconditionA=0 *CODE has been entered.A=1 *LINE has been entered. For further information, refer to theReference Manual part 1 .A=224-255 the indicated Unknown OSWORD has been called.On Exit: A, X and Y should be the same as on entry and the user routine shouldend with an RTS instruction.KEYVThe instruction KEYV is used to read the keyboard and it is this instructionthat informs the MOS just how much work to do on the keyboard. The requiredoperation is indicated by the status bits C (carry) and V (overflow). Normallythese are set and serviced by the MOS. However, by redirecting this vector theuser can invoke, supplement, or replace the normal MOS keyboard scanning, forexample, to add an alternative keyboard. The on the selected mode.The selection of video bandwidth and data format is performed by programmingthe VIDPROC. The cursor size and position is also controllable by VIDPROC.Special measures have been taken to ensure correct cursor operation in theTeletext modes.TeletextThe Teletext modes do not generate a bit mapped display, but a character cellone. The character/graphics ROM within a SAA5050 device generates RGB signalsaccording to the desired character/graphics information within the reservedmemory space. Each byte of memory is therefore just a definition of thecharacter/graphics symbol required.Other SAA505X devices may be used when different languages are required. Only1 Kbyte of memory is needed for either of the Teletext modes, although 20K isreserved for it in mode 135. The MOS uses the spare 19K to speed upinter-filing system file transfers but the user may use this memory if no suchtransfers are to be done. VIDPROC has to be re-programmed to use the SAA5050RGB outputs. The 6845 is still used to generate the cursor. As a delay of 2.75ms will occur between reading a character from RAM and outputting theappropriate RGB signals, the 6845 has to be programmed accordingly. The'start' of screen signal is given a 1 .5-byte time offset and the SAA5050 hasa further one-byte time offset to restore the correct cursor/data phase.VIDPROC has further adjustment which allows for the cursor to be adjusted topixe accuracy.Hardware ScrollScrolling may be achieved in any mode by re-programming the 6845 start ofscreen address to an integral number of video lines further down the memory mapthan the nominal start of screen. This causes the linear address generator toattempt to display an end of screen, which is out of the reserved video area.To overcome this effect, hardware scrolling is provided with a variable addresswrap-around. When the address generator would otherwise attempt to accessout-of-screen RAM, its addresses are modified to point to the gap between theoriginal start of screen and scrolled start of screen. When this is done, onlythe end of screen needs to be written over in RAM. (If this is not done, theentire screen appears to roll-over). The amount of modification to be used iscontrolled by two nodes; C0 and C1.PAGE: 44Video OutputThree outputs are provided for displaying video data. These are:a) PAL/NTSC encoded, UHF carrier. On channel 36 with 1.5mV into 75 ohm.b) Composite video. This is a 1v peak-to-peak signal.c) Digital Red-Green-Blue (RGB) - these are approximately 75 ohm outputs.For use with NTSC, the modulator has to be changed from UM1233/E36 to a VHFequivalent. Provision is made for selection of either one of two channels withVHF. A Molex type link has to be inserted for this.Flow chart not reproducedPAGE: 45Control RegistersThere are two control registers. The first contains miscellaneous controlfunctions, the other dictates the contents of the palette.Table not reproducedNotesbit 0 is re-programmed by the MOS at intervals to cause physical flashingcolour to alternate between its standard values and the (binary) logicalcomplement.bit 1 dictates whether the RGB signal supplied to the external buffers comesfrom the palette output or the Teletext character generator.bits 5-6 The cursor is 'on' for a number of byte-times, depending on the screenmode.PAGE: 46Palette Control Register (write only)bits 0-3 - physical colourbits 4-7 - logical colourThese are programmed together so that a certain physical colour is associatedwith a particular logical colour.In two colour modes, bit 7 dictates the colour- Eight locations must be programmed.In four colour modes, bits 7 and 5 dictate the colour- Four locations must be programmed for each logical colour.In eight colour modes, Bits 7 to 4 dictate the colour- One location must be programmed for each logical colourThe principle is that the remaining locations must be set to the same value asthe selected logical colour. If bits 7 and 5 in a four colour mode were 0, 1and phyvector can also be used to al lowkeyboard scanning when the interrupts have been switched off. On entry.If C=0 and V=0 then the SHIFT and CTRL keys will be read, returning N=1 ifCTRL is pressed and V=1 if SHIFT is pressed.If C=1 and V=0 the keyboard is scanned as described by OSBYTE 121.If C=0 and V=1 the key-pressed interrupt is serviced. This causes OSBYTE &78 tobe performed which reads the character corresponding to the pressed key intomemory.If C=1 and V=1 normal keyboard scanning will take place unless OSBYTE &C9 hasbeen used to disable it. This entry is made once every 10ms until all keydepressions have been removed. This processing includes SHIFT , SHIFT LOCK,CAPS LOCK and CTRL.PAGE: 92VDUVA number of VDU control sequences are 'unknown7 to the MOS , this means thatthe MOS has no internal routines to which they correspond and therefore itpasses control via VDUV to another code that may be able to deal with it.Those listed below are not the only unknown VD U codes but are merely thosenot previously assigned to other purposes. The Reference Manual Part 1 has afull list of the assignments.VDU 23, <28 to 31 >. This is used to provide up to 8 further parameters all ofwhich must be supplied, even if they are zero.VDU 25, <240 to 255>. These are the unknown graphics plot commands. If a VDU25 command is made in a non-graphics area VDUV will be used.VDU 25, <28 to 31>. Currently these are undefined.All unknown VDU calls are indicated by the C (carry) flag.On Entry.C=0: Unknown PLOT (VDU 25) command. The parameters are stored in VDUvariables 31 to 35 and can be read by OSBYTE &A0.VDU variable Contents 31 command number 32 co-ordinate X least significant byte 33 co-ordinate X most significant byte 34 co-ordinate Y least significant byte 35 co-ordinate Y most significant byteThe co-ordinates will already be scaled into internal pixel co-ordinates.C=1 : User defined ASCII command. A= the command number, the remaining eight variables are in VDU variables 27 to 35.In non-graphics modes the parameters will be stored as in C=0 given above. Theco-ordinates will not be scaled to internal co-ordinates in text modes becausethey have no meaning.On Exit:If the code is unknown to you the program flow should be returned via the OLDcontents of VDUV , otherwise use an RTS to terminate the code.PAGE: 93UPTVThe User Print Vector (UPTV) is provided for user printer routines. There aretwo ways of enabling this vector, by using *FX5,3 or by default using theCONFIGURE PRINT 3. U PTV is re-directed to point to user printer controlroutines. This facility is especially useful if the printer has specialfeatures which cannot be accessed by the standard printer drivers. Printersoften have their more powerful features invoked by sending an character followed by a number of characters which specify the parameters tobe used. The substitute printer driver can translate the special charactersinto the required command sequences. The following figure shows the flow ofdata under these circumstances.Drawing not reproducedPrinter data flowUPTV can be called when another printer driver is active, as shown below. Ifthis is the case control should be returned via the old contents of UPTVrather than terminating with RTS.In the following cases, when U PTV is used, it is the responsibility of theprinter driver to manipulate the computer's parallel printer port directly orto output serial data via the RS423 stream. The A-register notifies the printerof the required operation and on exit the carry flag is used to indicate aresult.PAGE: 94EntryconditionA=0 the driver is entered this way once every 10ms, unless it has indicatedthat it is dormant, which is described below. The driver should ensure that theACKnowledge line of the printer is active (high) and read a character from thebuffer using OSBYTE &91 . After any necessary translation the character issent to the printer.On Exit the driver should declare itself dormant if the buffer is empty byusing OSBYTsical colour 0,1,1,1 was to be written to this location, then 0,1,1,1must be written to all logical colour locations obtained with the fourcombinations of bits 6 and 4 while 7 and 5 are held as 0,1.The Cathode Ray Tube ControllerThe Cathode Ray Tube Controller (CRTC) is the heart of the microcomputer’svideo display circuitry. Its primary function is to display all video data inthe memory on a raster scan display device i.e. a television or a monitor.The CRTC chip used in the Master Series of microcomputers has sixteenregisters, which can all be accessed by the command VDU 23,0. Themanufacturer's data sheet gives the exact effect of the registers, and onlythe default values for each screen mode and the two control bits HS0 and HS1in the slow bus control latch are listed here. The bits HS0 and HS1 affect thescrolling function by extending the maximum address in the display memory map,as seen by the CRTC. Note all the numbers are in Hexadecimal.PAGE: 47CRTC chip registersTable not reproducedNotes1) These only apply if the screen position has not been modified by*CONFIGURE,Or a subsequent *TV command.2) These only apply if the interlace has been turned on by *CONFIGURE, or asubsequent *TV command.3) These values are only valid before hardware scrolling has been used.4) On reset, these registers are set to the screen start address, but theactual position will depend on how much screen output has been generated bylanguages, filing systems etc.PAGE: 485) Light pens can be connected either to the Analogue Port at the rear of themachine, or to either of the Cartridge Sockets just behind the keyboard. A low pulse on any of these connections to the light pen strobe will cause thecurrent scan position to be latched in the light pen position registers, R16and R17. The accuracy of the measurement will depend on the sensitivity of thelight pen. The figures given should be subtracted from the R16,R17 contents toyield the actual screen position, assuming ideal optical conditions. Theadjustment arises out of the different screen start addresses. The final X,yco-ordinates are:X = ((R16,17 - Offset) DIV (characters per line))/Light Pen Cell ModifierY = (R16,17 - Offset) MOD (characters per line)These offsets are only valid before hardware scrolling has been used. For thisreason it is often advisable to restrict light pen use to text or graphicsusing graphics mode. The Light Pen Cell Modifiers are necessary as the 6845 isclocked at different clock speeds in different modes, so in a given time, the6845 sees a different number of character cells from the one the viewer sees.The modifiers allow this to be taken into account.6) Each character cell is eight bytes deep as the 6845 imposes this format onthe memory map; so each entry in this line of the table is the number ofcharacter positions multiplied by eight. This figure can be used to establishthe start and end address of any scan row, given the screen's start address.7) The VIDeo PROCessor (VIDPROC) control register's least significant bit ischanged in all modes except Mode 7 to cause the colours to flash.CRTC MultiplexerThe CRTC Multiplexer converts the CRTC's eighteen-bit address into twoeight-bit addresses for the row and column parts of the DRAM's video cycle. Italso provides the hardware scroll logic to keep the addressed memory withinthe screen's 20Kbyte boundaries.PAGE: 49Internal TimingThe device uses a slightly delayed version of the DRAMs' nRAS strobe to selectbetween the row and column parts of the address.Hardware ScrollThe hardware scroll address modification as described in the section on 6845register values (MOS chapter) is performed by logic within this device. Someof the CRTC address lines are used in a non-standard way. The MA13 line isused as a 'Bit-Mapped or Teletext' mode indicator and is used to modify theaddress scan accordingly.Refresh ControlIn the bit-mapped modes, the memory is scanned often enough to render explicitrefresh unnecessary. In the Teletext modes, the addresE &7B followed by an RTS. This enables the printer driver to bechanged if necessary and prevents the MOS from wasting time by sending10ms calls to an empty buffer.A=1 the driver has previously been dormant and one or more characters had beenplaced in the buffer. The reading and printing of the characters is as for A=0.On exit, the carry flag signals the buffer state to the MOS (C=1 shows that thebuffer is empty).A=2 ASCII code 2 (Ctrl-B) has been sent to the driver. Except in shared systemswhere it is used to claim a remote printer, the driver should be made to ignorethis code.A=3 ASCII code 3 (Ctrl-C) has been sent to the driver.A=4 not used.A=5 the printer type has been redefined using OSBYTE 5. The new printer drivernumber is in X.FSCVThe vector FSCV provides access to a number of miscellaneous filing systemfunctions. The required function is indicated by a reason code in theaccumulator.Unless indicated, the registers are not defined and interrupts may be enabledduring the call.EntryConditionA=0 A *OPT command has been issued with X and Y as parameters.A=1 check for End Of File (EOF) - file handle in X-register.If on exit EOF is true X=&FF, otherwise X=0.A=2 * / command has been issued. The filing system should try to*RUN the file named after the / symbol.A=3 attempt to *RUN specified file. X and Y contain the lsb and msbrespectively of the address of the ASCII string containing the name of thefile. This call is originates when a * command has been rejected by all ROMS.If the file cannot be *RUN, the message 'BAD COMMAND7 will be issued ratherthan 'FILE NOT FOUND'.PAGE: 95A=4 X and Y point to the name of a file to be *RUN.A=5 X and Y point to a string containing the parameters of a *CAT command thathas just been issued.A=6 another filing system is being invoked so *SPOOL ana *EXEC files should beclosed and other open files should be ensured.A=7 the filing system is being interrogated to supply its range of filehandles.On Exit X= the lowest handle, y= the highest.A=8 an OSCLI command has been issued. This call permits filing systems toensure the integrity of their media.A=9 a *EX command has been issued and the information is sent to the outputstream.A=10 *INFO command has been issued The information is sent to the outputstream.A=11 *RUN a file via LIBFS.INSVThe INSV Vector can be used to invoke a custom routine to insert charactersinto a specified buffer or to provide a much larger buffer.On entry A= and X=.On exit C=1 if the buffer is full. (The MOS will abort or retry in response tothis.)REMVThe REMV vector may be used to invoke a routine to remove a character from thebuffer or simply to examine the character.On entry X= the buffer number, V=0 to remove the next character from thebuffer orV=1 simply to examine the next character.On exit C=1 if the buffer was empty, X is preserved, Y is the character to beremoved, or A=the character that was examined.CNPVThe CNPV vector points to a routine to count the number of characters in abuffer orto flush that buffer.On entry X= the buffer number. To count the characters set V and C to 0 and tocount the spaces set V to 0 and C to 1. To flush the buffer set V to 1 .On exit the values of V and C are preserved. If a count has been made, X= countleast significant byte and y=count most significant byte.PAGE: 96NETVThe NETV vector usually points to the routine which initialises the AdvancedNetwork Filing System (ANFS) and thus permits the use of utilities like *VIEWand *REMOTE. The NETV facility can be used by user code for this purpose or torestrict the ECONET access to a particular part of the system by filtering outunwanted commands. On entry the function to be performed is contained in A.EntryconditionA=0-3,5 printer commands, same as for UPTV. The number for the ECONETprinter driver is 4.A=4 OSWRCH has been called.On exit the character will be output if C=0, otherwise C=1.A=6 OSRDCH has been called.On exit the network should put the characteses of non-displayedlocations (as accessed in the 24ms per line when the display is inactive) aremodified to produce sequential scanning and hence maintain the refresh.MultiplexingThe address is output, one half at a time for each of the Row and Columnaddresses. One of four eight bit fields may be selected:1) Bit mapped display - low order address2) Bit mapped display - high order address3) Teletext display - low order address4) Teletext display - high order addressThe VDU driverThe VDU Driver is extensively covered in Part 1 of the Reference Manual.However, by programming in machine code, the hardware may be accesseddirectly to give additional display modes, such as a 640*512 MODE. This is atwo-colour mode which uses both the main and shadow screen memories to storealternate half-frames of an interlaced synchronisation and video picture. Themethod used is as follows:PAGE: 501. Select MODE 02. Program the CRTC for interlaced sync. and video.3. Set the EVNTV vector to point to your code.4. Enable the vertical synchronisation event.5. Use OSBYTE 70 (X=1 ) (*FX 112, 1 ) to select the half-frame to be drawn.6. Draw the half-frame.7. Use OSBYTE 70 (X=2) (*FX 112,2) to select the second half-frame.8. Draw the second half-frame.9. Use OSBYTE 71 (X=1,X=2) (*FX 113,1 and *FX 1 13,2) to select alternate screens on alternate vertical synchronisation events.The program will alternate the half-frames correctly but should provide thefacility to reverse the display sequence as the hardware may present the twohalf-frames in the incorrect phase.The display may be distorted if any software disables the verticalsynchronisation event.PAGE: 51OSBYTE &75 (1 17) is used to read the VDU status byte, and puts its currentvalue into the X register. The bits in the result have the following meanings.VDU status - bit 0 printer output enabledbit 1 scrolling disabledbit 2 paged software scrolling enabledbit 3 text window is currently defined this is set up by VDU 28 and cleared by VDU 26bit 4 shadow screen selectedbit 5 printing at graphics cursor enabledbit 6 cursor editing mode enabledbit 7 VDU is disabled via VDU 21.PAGE: 527 THE USER PORTThe User Port provides the following facilities:Eight-bit bi-directional data port with optional handshakingProgrammable pulse generatorProgrammable frequency generatorPulse counterSynchronous/asynchronous SI PO/PISO shift registerIt appears as a set of memory-mapped locations and is accessed using OSBYTEs&96,&97 (150,151). As the parallel printer port is controlled by the same 6522versatile interface adapter (VIA) chip, care should be taken to avoid conflictsbetween the two applications. The 6522 registers that control the User Port aredescribed here, bit-by-bit. DO is the least significant bit, D7 is the mostsignificant bit. The User 6522 VIA has a base address of &FE60TimersTwo sixteen-bit counter/timers are provided. They are designated T1 and T2.Each consists of a sixteen-bit decrementing counter, one or two eight-bitlatches and some control logic. The latches are used to store the values thatwill be loaded into their respective counters when a particular event occurs.The modes of operation are determined by the Auxiliary Control Register.User VIA Address MappingOffset Function0 User Port Data Register2 User Port Data Direction Register4 T1 - Low Order Counter/Latch ( R/W)5 T1 - High Order Counter (R/W)6 T1 - Low Order Latch (R/W)7 T1 - High Order Latch (R/W)8 T2 - Low Order Counter/Latch (R/W)9 T2 - High Order Counter (R/W)10 Shift Register12 Peripheral Control Register13 Interrupt Flag Register14 Interrupt Enable RegisterPAGE: 53User Port Data RegisterUser Port access. Bit PB0 on the User Port corresponds to the data bit D0whilst PB7 corresponds to D7. Control lines CB1 and CB2 can be programmed tobehave as handshake lines. CB1 acts as Data Acknowledge. CB2 acts as DataReady. For example, if the following connections are made between two MasterSeries computers (A andr into A.A=7 OSBYTE has been called. The values of A, X, and Y are stored at&00EF to &00F1 .If on exit the call is passed to OSWORD then V=0 , otherwise V=1.A=8 a line has been read by OSWORD 0. ANFS can now take overOSRDCH.INDirect VectorsThere are three indirect vectors available, these are IND1V , IND2V and IND3V.The indirect vectors are used to access sideways ROMS and the Terminal Emulatoruses IND1V and IND2V.Note on the entry points for these vectorsThese routines are not provided with entry points, but the MOS versions of themterminate with an RTS. They should be called by. JSR ' ' ' ' .callroutine JP ()This performs a Jump to Subroutine and then an indirect Jump.PAGE: 97Time-dependent functionsIn the previous section on time-independent functions some functions whichmight have been expected to be time-dependent were described. This was becausesoftware routines may be used to simulate tasks which are normally dictated byexternal events, a technique which is frequently used to develop real timesoftware.Real time events usually occur at a high frequency compared with the timetaken to run the service software and also they may occur fairly quickly inrelation to other events.Real time events are initiated by hardware, either internal or external, whichpasses an interrupt request (IRQ) to the CPU. An IRQ is generated by pullingthe IRQ pin of the CPU low. As all devices are connected to this pin, the MOShas to interrogate them to determine which device was thesource of the interrupt. When the source device has been identifiedthe MOS will service it and perform avectored subroutine call via EVENTV to pass on the information.If the CPU cannot determine the source of the interrupt it offers it to eachof the sideways ROMS or RAMS. In this way hardware which uses interrupts (forexample, on the 1 MHz bus) may be accommodated. Whichever page the controllersoftware is in, it will ultimately be notified of the interrupt.The time this takes may result in data being lost. In order to alleviate thisproblem the computer can be set up to give the user the chance of identifyingan interrupt before it is passed round the computer, or back to the MOS.EVENTVThe entry parameters for EVENTV are detailed in the previous section. If anyextra hardware has been added to the computer, it will generate an interrupt tocause the MOS to pass control via EVENTV with A=9, if it has not been able todetermine the source of the interrupt itself. Note this only happens if theUSER Event has been enabled with OSBYTE &E,9.In order to process the IRQs quickly, it may be necessary to process thembefore they are passed round the sideways ROMS, or in some cases before the MOSservices them. Two vectors IRQ1V and IRQ2V are provided for this purpose.Function vector name locationTo access the highest IRQ1V &204priority devices.To pass the event IRQ2V &206round paged ROMSPAGE: 98All the user interrupt routines should be as short as possible, the recommendedmaximum is 0.5ms. This is particularly important when using IRQ1V because thisservices the interrupt before the MOS. As an example consider the operation ofRS423 at 19,200 baud, which corresponds to one byte being transmitted every416ms. As all interrupts would have to pass through user code pointed to byIRQ1V before the MOS could deal with them, a 2ms service routine would occupythe time for 4.8 bytes. This would lower the average speed to about 4000 baud.When the MOS is selected by IRQ1 V (which is usually the case), it examinesdevices in the following order.1. The 6850 ACIA which controls the RS423 interface and the cassette data.2. The System Versatile Interface Adapter (VIA) which controls the verticalsynchronisation, the interrupts, the light pen (if included in the system),the AID converter, the system timer, the sound system, the keyboard and thereal time clock.3. The User VIA which controls the User Port and the Parallel Printer Port.Note the manufacturers data sheets B)Computer A Computer BPB[0:7] to PB[0:7] CB1 to CB2 CB2 to CB1Ground to Groundwhen the interrupts are enabled, writing a byte to the User Port in A willcause an interrupt to be generated in B. When B reads the data from its UserPort, A will be interrupted to indicate that the data has been taken. The datatraffic will also work in the other direction.The manufacturer's data sheet should be consulted for detailed timinginformation.User Port Data Direction RegisterEach bit in this register acts as a flag for the corresponding User Port bit.If set it will be an output, if clear an input.Timer 1 Low Order Counter/Latch (R/W)Read - the T1 low order counter is read and the T1 interrupt flag (in theInterrupt Flag Register) is cleared.Write - the data written into this latch is transferred to the T1 low ordercounter after either the T1 high order counter is written to, or the T2counter underflows through zero in the free-run mode.Timer 1 High Order Counter (R/W)Read - the T1 high order counter is read, but the T1 interrupt status is notaffected.Write - the data written into the latch is stored and transferred into the T2High Order counter at the next system 1 MHz high transition. T1 low orderlatch is transferred to T1 low order counter at the same time. This actioneffectively starts the counter and the T1 interrupt flag is clearedaccordingly.PAGE: 54Timer 1 - Low Order Latch (R/W)Read - the value in the T1 low order latch is read. T1 interrupt status is notaffected.Write - equivalent to writing to Offset 4.Timer 1 High Order Latch (R/W)Read - the last value written is read back.Write - the value written is stored, but is only transferred to the T1 highorder counter when T1 underflows in free-run mode.T2 Low Order Counter/Latch (R/W)Read - T2 low order counter is read and the T2 interrupt is cleared.Write - the data written is stored in the T2 low order latch.T2 High Order Counter (R/W)Read - T2 high order counter is read.Write - the data is written directly into the T2 high order counter. Thiscauses the value in the T2 low order latch to be transferred into the T2 loworder counter and the T2 interrupt is cleared.Shift RegisterA multi-function register controlled by the Auxiliary Control Register atOffset 11 . It is a left-shift, circulating register, i.e. data is shifted infrom bit 0 towards bit 7 and when shifting out, has bit 7 connected to theinput of bit 0. It has eight modes of operation which are in no way related tothe screen modes.Mode 0 - Static Shift Register.Read - the value shifted into the shift register is read.Write - the shift register will contain the value written.Shift - the data on CB2 will be shifted in on CB1 positive transitions.Interrupts - the shift register interrupt is disabled.Mode 1 - Data Shifted in by T2.Read - the value shifted into the shift register is read. Shifting will start.Write - the shift register will contain the value written. Shifting will start.PAGE: 55Shift - data is shifted in on CB2a) after a read/write operation with the SR interrupt clear,b) after T2 times out following a read/write with SR interrupt SET. Shiftingwill occur for eight T2 time-outs.Interrupts - the SR interrupt will occur after eight T2 time-outs.Note: In this mode CB1 is clocked with the T2 time-out. This is to provide aclock for the external device providing the data. Data is shifted in on the CB1negative edge, but is sampled (latched) on the CB1 positive edge. For thisreason, the external device should be clocked on the CB1 negative edge.Shifting stops after the eighth shift.Mode 2 - Data Shifted in by the system 1 MHz clock.This is similar to Mode 1 except that CB1 clock is the system 1 MHz clock,divided by two.Mode 3 - Data Shifted in by externally provided CB1 clock.This mode is used when data is provided by an asynchronous source from which aclock is derived.Read - the value shifted into the shift register is read.Write - the shift register will contain the value writt for these devices should be consulted fordetails of the interrupt status registers of these devices.PAGE: 9912 DUAL PROCESSORSYSTEMSSecond processor architectureTo enhance the computing power of the BBC microcomputer, Acorn has adopted atwo-processor architecture. The base, or host, processor performs most of theI/O routines, such as communicating with the keyboard and filing systems,whilst the language, or parasite, processor provides the raw computing powerto perform applications.The host processor is a 6502 in the Model B and a 65C12 in the B+ and MasterSeries. Acorn language processors range from the 8-bit 65C02 and Z80, throughthe 16/32-bit 80186 to the 32-bit 32016 and Acorn RISC Machine. Third-partymanufacturers supply Z80, 6809 and 68000 systems. (The ARM second processorarchitecture is slightly different from that of the other language processorsas it is provided with its own peripheral controller chips and communicatesdirectly with the video and audio outputs. However, filing and other I/Ooperations still take place through the host.)Each processor runs independently of the other and is provided with its ownclock and memory chips. The two systems communicate with one another over a2MHz asynchronous bus, known as the Tube, which is controlled at each end bya custom interface.Since the language processor does not need to control complex peripheralsdirectly, it can manage with only a rudimentary operating system. This MOS isrequired simply to initialise the system on RESET and to implement calls suchas OSBYTE and OSWORD. The base processor then performs the requiredoperations and returns the result to the language processor.Not all the MOS calls are fully implemented. For example, filing systemcontrol is carried out by the base processor, so FSCV is not required and, inthe Master Turbo for example, points to a 'Bad' error routine. the defaultsetting of EVNTV and the user-set vectors point to an RTS opcode. Whilst theoperation is being carried out, the language processor can continue executingits application.Operating system calls are implemented by transferring the call and itsparameters to the base processor, which performs the desired operation andsends a response back via the Tube. To speed matters up, only the minimumrequired number ofPAGE: 100parameters is transferred. For instance, with OSBYTE calls 0-&7F , the y-parameter is omitted. For those calls in which the carry status is asignificant part of the result, it is transferred across the Tube by performinga shift operation in the source processor and a complementary shift operationto prime the carry flag in the destination processor.Data transfers are achieved by generating interrupts in the second processor.Different routines are provided for different operations, the appropriate onebeing selected by resetting the NMI vector (which is feasible, since afterRESET all READ operations are directed to RAM).Usually the language processor is provided with a clear block of contiguousread/write memory. Its boot operating system is in ROM which is mapped into thetop of the processor's address range. On RESET the MOS is copied from ROMinto RAM and awaits initialisation via the Tube. Processors such as the 80186,which run industry standard operating systems, have a ROM-based startup butload the remainder in from disc.When functioning as an I/O processor, the base processor installs Tubecommunications routines in the regions of low memory which are normallyallocated to the active language. (addresses &0016-&005C in Page 0 and Pages4-7). These communications routines have language and service entry pointssimilar to those of paged ROMs and also a data entry point which is used oncethe Tube has been initialised.If the second processor is added externally it is referred to as a 'SecondProcessor' and one added internally as a 'Co-Processor'. Except whereindicated, references to a co-processor apply equally to a second processor.The TubeThe Tube provides the means for the language and l/Oen.Shift - data is shifted in on CB2 at the system 1 MHz pulse after the CB1positive transition.Interrupts - the shift register interrupt is set after 8 data bits have beenshifted in. It is reset at the next read/write of the shift register.Note. Due to the shift-in timing, it is recommended that the incoming data rateshould not exceed 250kHz, thereby allowing for the asynchronism between thetransmitting and receiving units. The actual data rate is more likely to belimited by the speed with which the 'register full' interrupt is serviced; theshift register keeps shifting whether or not it is serviced, so data may belost if the user's program does not respond in time.Modes 4 and 5 - Data Shifted out by T2.Read - the current shift register value is read. Shifting will start.Write - the shift register will contain the value written. Shifting will start.Shift - data is shifted out on CB2a) after a read/write operation with the SR interrupt clear.b) after T2 times-out following a read/write with S R interrupt set. In Mode 4,shifting occurs at every T2 time-out. In Mode 5, shifting will occur for eightT2 time-outs and then stop until the interrupt is serviced and new data isloaded. Interrupts - the SR interrupt will occur after eight T2 time-outs.PAGE: 56Note: In this mode CB1 is clocked with the T2 time-out. This is to provide aclock for the external device sampling the data. Data is shifted on the CB1positive edge, but should be sampled by the external device on the CB1 negativeedge. For this reason, the external device should be clocked on the CB1negative edge. Shifting stops after the eighth shift in Mode 5 but iscontinuous in Mode 4.Mode 6 - Data Shifted out by the system 1 MHz clock.This is the shift out equivalent of Mode 2.Mode 7 - Data Shifted out by externally provided CB1 clock.This is the shift out equivalent of Mode 3. The same restrictions to data rateapply.Auxiliary Control Register (R/W )Controls the shift register mode, Timer 1 . Timer 2 and the Port A B latching.It is divided into three fields(1) Port LatchingBit 0 enables/disables latching of the Printer port. This bit must bemaintained at all times.Bit 1 enables/disables latching of the User Port. A logic 1 will enablelatching. CB1 acts as a strobe to latch the data.(2) Shift Register ControlBits 4,3,2 Function 0 0 0 Mode 0 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7(3) Timer 2 ControlBit 5 0 - interrupt when T2 decremented to zero1 - decrement T2 with each pulse input to PB6. Interrupt when T2=0,then re-load and continue counting, so generating an interrupt stream.T2 high order counter must be written after every T2 interrupt to enablethe next interruptPAGE: 57(3) Timer 1 ControlBits 6,7 Operation0 0 After loading T1 , it will generate a single interrupt after decrementing to zero.0 1 After loading T1 , it will generate a stream of interrupts; one whenever it counts down to zero.1 0 As 00 but output a single pulse on PB7 as well as the interrupt.1 1 As 01 but generate a stream of output pulses as well as the interrupts,Note: When Timer 1 mode 1 1 is selected, PB7 will change polarity every time T1counts down to zero. This means that it will output a waveform of frequency.PB7 frequency = 1/(*2)Peripheral Control Register.The most significant nibble dictates the function of the CB1, CB2 controllines, whilst the least significant nibble controls CA1, CA2. The lattershould not be touched as it may interfere with correct parallel printeroperation. Whenever writing to this register, ensure that the leastsignificant nibble is preserved.CB1 Interrupt ControlBit 4 0 - generate an interrupt on a CB1 negative edge. 1 - generate an interrupt on a CB1 positive edge.CB2 ControlBits 5,6,7 Operation0 0 0 CB2 will generate an interrupt on its negative edge0 0 1 CB2 as above, independent mode0 1 0 CB2 will generate an interrupt on its p processors to communicatewith each other. The Tube comprises a pair of proprietary chips coupled to therespective processors and communicating with one another over a 2MHzasynchronous bus.The Tube chip is a semi-custom integrated circuit designed to overcome theproblems of interlacing between processors running at different instructionand bus cycle rates. The language processors have different clock rates fromthat of the base processor and may also have incompatible instruction sets,which prevents the possibility of direct (synchronous) coupling between them.The Tube chip is therefore provided with the buffers and latches necessary toimplement asynchronous coupling.PAGE: 101The Tube has two one-byte wide ports. One port is for the host and the otherfor the parasite. The ports provide access for the host and the parasite to anumber of registers. The Tube chip is located on the language processor circuit board and isconnected to the host by a byte wide bus.The Tube protocols allow the language processor to have full access to thefiling system, the VDU Driver, the RS423 or any other 1/O devices connected tothe microcomputer.The protocol is a set of software rules for passing data across the Tube chip.The Tube protocols are partly held in the M0S and partly in the languageprocessor. Data is referred to as being passed 'across the Tube'.PAGE: 102Tube ProtocolsThe protocols are sequences of read/write operations to the Tube chip thathave to be performed in order to pass data between the host and parasite. Somesequences enable an application in the parasite to control the host, requestdata and transmit it to the outside world and are usually initiated by firmwareroutines in the parasite. These in turn will have been called by theapplications program running in the language processor RAM.Other sequences are used to pass events, errors and effect low-level blocktransfers; these are initiated by the host. There are sixteen differentsequences, each designed for a specific task. Note that there are two callswhich are only designed for use in the host to ensure compatibility withprevious BBC Microcomputers. Three others are not intended to work 'across theTube' and are only mentioned here for completeness. The full list of sequencenames and their purpose follows:OSBYTE Execute a MOS routine requiring up to a three byte argument.OSWORD Execute a MOS routine requiring a parameter block.OSCLI Interpret a * command.OSRDCH Read a character from the input stream (e.g. RS423, keyboard).OSRDSC Read from the screen. (not available to language processors)OSWRCH Write a character to the output stream (e.g. RS423, screen).OSNEWL Write LF followed by CR to the output stream.OSASCI Write a character to the output stream, or LF followed by CR if thecharacter is CR.OSWRSC Write to the screen. (not available to language processors)OSFIND Open or close a file for byte access.OSFILE Load or save a file.OSARGS Load or save data about a file (e.g. sequential pointer, extent).OSGBPB Load or save part of a file.OSBPUT Save a byte to a file.OSBGET Load a byte from a file.OSEVEN Generate an event. (not available to language processors)GSINIT Initialise GSREAD string. (not available to language processors)GSREAD Read a byte from a string. (not available to language processors)The names are for reference only. The form of parameter(s) used by eachsequence is listed in the Reference Manual, Part 1. Whatever microprocessor isused in the parasite, a given sequence with given parameters will always workin the same way.PAGE: 103In this text, 'HÞP' indicates the passage of data from the host to theparasite and 'PÞH' shows the passage of data from the parasite to the host.Each protocol consists of read/write accesses to the Tube registers,conditional branching based on the register contents, and the copying of thecontents into memory. The Tube chip appears, to both the host and the parasite,as a collection of memory or 1/O mapped registers. There are four independentbi-dirositive edge0 1 1 CB2 as above, independent mode1 0 0 CB2 provides the 'Data Ready' handshake output.1 0 1 CB2 provides a single high-going pulse.1 1 0 CB2 goes to a 01 1 1 CB2 goes to a 1Independent ModeWhilst reading the User Port Data Register would normally clear the interruptrequest that transitions on CB2 have created, in the 'independent modes' theseinterrupts have to be cleared by directly clearing the appropriate bits in theInterrupt Flag Register.Note that the bits 0, 1 ,2,3 perform a similar function for CA1 and CA2.PAGE: 58Interrupt Flag RegisterThe CPU has to be able to determine which function of the User Port isgenerating an interrupt. This register has a bit representing each of thefunctions that can do this. Even if an interrupt source has been disabledusing the Interrupt Enable Register, it can still set its appropriate flag inthis register. A set bit indicates that the function is trying to generate aninterrupt.Register bit set when... cleared when...0 CA2 active edge occurs Printer port is accessed1 CA1 active edge occurs Printer port is accessed2 Shift Register completes Shift Register is accessed 8 shifts3 CB2 active edge occurs User Port Data is accessed4 CB1 active edge occurs User Port Data is accessed5 T2 times-out Read T2 low order OR Write T2 high order6 T1 times-out Read T1 low order OR Write T1 high order7 Any interrupt is set All interrupts are clearNote that bit 7 is designed to enable fast interrupt control. It is onlynecessary to test bit 7 to find out if any of the functions are generating aninterrupt request. The CPU's BIT operation will cause its negative status bitto be set if bit 7 is set in this register.Interrupt Enable RegisterFor each bit in the Interrupt Flag Register to cause an interrupt, thecorresponding bit in the this register must be set.Register bit Enables the interrupt from0 CA21 CA12 Shift Register3 CB24 CB15 Timer 26 Timer 17 GlobalIf the Global bit is clear, then every set bit in the register disables thecorresponding interrupt request. If it is set then every set bit in theregister enables the corresponding interrupt request.When this register is read, Bit 7 will be set and other bits will be aswritten.PAGE: 59Example of motor controlFor example, to control a three axis machine which uses stepper motors, Timer 1frequency generator output may be used to provide stepping pulses to motorphase sequence generators. Other PB lines can provide forward/backward controland move/hold controls. This means that all three motors can be rotating atonce. The Timer 2 pulse counter can be used to count the number of pulses thathave been applied to the motors. Every time a T2 interrupt is generated, thosemotors which are enabled will have their positions (as stored in memory)updated by the CPU. Limit switches on each axis can be connected to over-ridethe 6522 outputs and logically ORed to generate an interrupt so that if anymotor tries to go 'off the end' the CPU will detect this and so prevent theoccurrence of any damage. The PB lines can then be used as inputs to determinewhich motor has gone to its end stop.MethodAssign the User Port pins :a) CB1 will be the global alarm (overrun) input.b) PA7 is the frequency generator output.c) PA6 is the pulse counter.d) PA5 is the Z axis enable/fault indicator.e) PA4 is the Z axis direction control/fault indicator.f) PA3 is the Y axis enable/fault indicator.g) PA2 is the Y axis direction control/fault indicator.h) PAl is the X axis enable/fault indicator.i) PA0 is the X axis direction control/fault indicator.To run the motors:PA7 must be a frequency outputPA6 must be a counter inputPA[0:5] must be outputsThus.Location Contents Comments 7 0&FE6A 0000oooo CB1 negative interrupt&FE6B 1110oooo Set up the timer controls&FE6E 1ooo1ooo Enable the T2 interrupt&FE62 10111111 Enable the outputs&FE60 XXDDDDDD Operate the motorso is the old contents D is the deectional communication paths, each of which consists of a one bytecontrol register and a one byte data register (which may have a one-bytebuffering). The roles of the respective registers are described below.Operating System UsageRegisters R1STATUS,R1DATA; R2STATUS and R2DATA are mainly for MOS data and command transfer under polled or parasite IRQ operation.Register 1 status (R1STATUS)The status of R1 DATA is indicated by this byte.BIT 7 6 5 4 3 2 1 0 DA1 NF1 P V M J I QWhen set to logic 1 :DA1 - Data Available in data register 1NF1 - Data register 1 is Not FullP - Set parasite reset active lowV - Enable two byte FIFO operation of R3DATAM - Enable parasite NMI from R3DATAJ - Enable parasite IRQ from R4DATA1 - Enable parasite IRQ from R1 DATAQ - Enable host IRQ from R4DATA (Not Used)Register 1 data (R1 DATA)HÞPA 1 -byte buffer is used by events in the host to generate IRQs to theparasite. Writing to this register will cause the parasite IRQ to be activelow. It is also used to pass on the ESCAPE condition.PAGE: 104PÞHThis is a 24-byte FIFO buffer and carries the parameters for OSWRCH. Note thatOSWRCH only uses a 1 O-byte parameter block, so a language processor can entera full plot command without having to wait for the host to remove each byte inturn. Although the Tube chip circuitry is designed to be able to interrupt thehost if the parasite writes to this register, this facility is not used on thehost, which will normally poll R1STATUS until the data becomes available.Register 2 status (R2STATUS)The status of R2DATA is indicated by this read only byte.BIT 7 6 5 4 3 2 1 0 DA2 NF2 1 1 1 1 1 1When set to logic 1 : DA2- Data Available in data register 2 NF2- Data register 2 is Not FullRegister 2 data (R2DATA)Register 2 initiates MOS calls which may take a long time or must notinterrupt hosttasks.HÞPThe host returns data as appropriate.PÞHThe parasite requests the task and then passes data as appropriate.Filing System UsageRegisters R3STATUS,R3DATA, R4STATUS and R4DATA are mainly used by filing systems for fast transfer under NM Is - may be used for high speedprotocols by 'claiming' the Tube (see section on the Host Protocols).Register 3 status (R3STATUS)The status of R3DATA is indicated by this read only byte.BIT 7 6 5 4 3 2 1 0 DA3 NF3 1 1 1 1 1 1PAGE: 105When set to logic 1 :DA3 - Data Available in R3DATA/Parasite NMI generatedNF3- Data register 3 is Not FullRegister 3 data CR3DATA)HÞP; PÞHThis is used for the fast data transfers. Note that the host can program it tooperate in a two byte mode.R3DATA and R3STATUS are used for the block transfers as a background task.For higher performance applications this register may interface to a DMAcontroller.Register 4 status CR4STATUS)The status of R4DATA is indicated by this read only byte.BIT 7 6 5 4 3 2 1 0 DA4 NF4 1 1 1 1 1 1When set to logic 1 :DA4 - Data Available in R4DATA/Parasite I RQ generatedNF4 - Data register 4 is Not FullRegister 4 data (R4DATA)HÞPWriting to R4DAT A sets the parasite I RQ. Reading R4DAT A clears the I RQ.The Host interrupts the second processor by writing a byte describing therequired action into R4DATA. The two machines then co-operate in passing dataacross register 4 until the job is done.The register set is also used to initiate the passing of an error string fromHost to Parasite. The Host interrupts the Parasite by writing an error codeinto R4DATA, the two machines then co-operate in passing the error stringacross R2DATA.PÞHR4DATA is used as a control channel to request block transfers through R3DATA.PAGE: 106PARASITE ProtocolsFrom the point of view of the language processor, the Tube protocols arepresented in the following generalised form:Wait until ready then...[Wait until [CONDITION 1] TRUE][Wait until [CONDITION 2] TRUE] Synchronising Phase[Wait until [CONDITION n] TRUE]THEN[Perform Task 1][Perform Task 2] [Perform Task m]ELSE Execution Phase [Perform Task a] [Perfosired actionPAGE: 60Timer 1 should be programmed with the value for the required operatingfrequency.To find out which motor has overrun:PA[0:5] should be inputsPA7 should be switched off whilst the overrun is checked.Thus:Location Contents Comments 7 0&FE6B 0010oooo Switch off Timer 1&FE62 10000000 Inputs to read the switches.&FE60 XXDDDDDD Read the switches.o is the old contents D is the desired actionOperation can now be returned to 'Running Mode'.PAGE: 618 THE SERIAL PROCESSORThe serial processor (SERPROC) is used in conjunction with the 6850 UART toprovide the RS423 and cassette tape interfaces. It contains a baud rategenerator, channel multiplexer and tone generator.UARTThe device responsible for providing most of the serial port functions is a6850 UART. This has all the receive/transmit and data formatting/error checkingthat is necessary for both systems. It is fully described in the March 1983edition of the Hitachi Microcomputer Databook.SERPROCThe ACORN proprietary part, SERPROC is effectively a multiplexer and baud rategenerator for the 6850. It also generates the phase-continuous transmissioncircuitry for use with the cassette interface.Buffer ComponentsThe RS423 transmit data and CTS lines are buffered by an AM26LS30 orequivalent. This provides a single ended transmission with slew rate limitedoutput. RS423 receive data and RTS is buffered by a mA9637AC or equivalent.Both buffers are connected with single-ended input configurations.Cassette data output from the SERPROC is buffered by a single, non-invertingoperational amplifier with a simple single pole filter, a.c. couplingcapacitor and current limiting output resistor.PAGE: 62Control Register Settings Bit # Function Parameters 0-2 Transmit Baud Rate 000 : 19200 100 : 9600 010 : 4800 110 : 2400 011 : 1200 101 : 300 011 : 150 3-5 Receive Baud Rate 000 : 19200 100 : 9600 010 : 4800 110 : 2400 011 : 1200 101 : 300 011 : 150 111 : 75 6 Channel Select 0 : Select Tape 1 : Select RS423 7 Cassette Motor Relay 0 : Contacts open 1 : ContactsNote. The Transmit and Receive baud rates both assume that the 6850 has itsclock divider set to divide by 64.Receive baud rate not used in cassette mode, but Bit 3 may control inversionof the Transmit data (VTI version of SERPROC)PAGE: 639 THE PERIPHERAL BUS CONTROLLERThe peripheral bus controller buffers data between the 65C12 CPU con the 'CD'bus) and the internal peripherals on the 'BD' bus, the external '1 MHz Bus'and the external 'Tube' interfaces (both on the 'ED' bus). It also contains atimer to generate a long delay after power-up.Internal TimingAll the necessary timing is synthesised from the system 8MHz and 1 MHz signals.Buffer ControlThe selected buffer path is determined by the RDY and FIT signals, as describedfor the I/O Controller, together with the system R/W signal.TimerThe timer is an eight-bit counter with an external oscillator, which is alsoused as the timer's output. The oscillator output is used to charge/dischargea timing capacitor. The use of a charge time constant which is 1% of thedischarge time constant causes the output (CHRG) to be low most of the time.When the input (TICK) crosses the threshold during an oscillation, the counteris incremented. When the terminal count is reached, the output is fixed high.The counter can only be reset by switching the power off. This timer wasoriginally designed to support the boost charge of nickel-cadmium batteriesfor the Real Time Clock.PAGE: 64I/O DefinitionPin Name No I/O Input Buffer Type Output Buffer TypeTICK 4 I CMOS SCHMITTNFIT 5 I CMOSR/W 6 I CMOSRDY 11 I CMOSNPRST 1 I TTL -DEN 2 I TTL -M1 29 I TTL -M8 31 I TTL -CHRG 3 0 - standardBRNW 7 0 - standardEM1E 8 0 - standardER/W 9 0 - standardED7 12 I/O TTLrm Task b] . . [Perform Task z] THEN[Wait until [CONDITION A] TRUE][Wait until [CONDITION B] TRUE] . . Completion Phase .[Wait until [CONDITION Z] TRUE]RETURN FROM PROTOCOLVectorsEach Acorn-supplied second processor has a simple operating system which .contains all of the routines necessary to implement the Tube communicationsprotocols. This operating system is ROM-based and is copied across into RAMwhen the second processor is reset.PAGE: 107As the Master 128 65C12 and the Master Turbo 65C102 co-processor are opcodecompatible, the entry points and vectors for a given OS call are the same ineach. This also applies to the 6502 second processor.Hardware DependencyHost Hardware :Hardware dependent calls should not be redirected, as user code in the languageprocessor cannot access the hardware (unless the user has set up a program inthe host to intercept, say, a standard OSFILE call and turn it into auser-defined OSWORD).Note that with the exception of the '1 MHz Bus', Cartridge Bus and User Port, Acorn does not support direct user control of hardware.Parasite Hardware:The only hardware available to a program in the parasite is the CPU, memory andTube. Redirecting, say, a VDU operation is of limited use. The exception tothis is if the user is running the program in a specially constructed(external) second processor which has perhaps its own ultra-high resolutiongraphics circuitry, or a signal processing system to which the host does nothave access.Non-Interrupt protocolsOSWRCHWait until R1 DATA not full, write character into R1 DATAOSRDCHWait until R2DATA not full, write RDCHNO (=&00) to R2DATAWait for data in R2DATA, top bit of R2DATA is 65C12 C-flag (validity bit)Wait for data in R2DATA, R2DATA is 65C12 A register (character read).OSCLIWait until R2DATA not full, write CLINO (=&02) to R2DATAFOR all characters in the command string (including terminating )DO [ Wait until R2DATA not full, write character to R2DATA ]Wait for data in R2DATA and read itIF this byte=&80 then code has been loaded into the language processorstore as a result of the command and it should be entered at the addressgiven by the last R4 protocol type 4 address. This means that anotherprotocol has been invoked by this one and has already finished.PAGE: 108OSBYTEIF osbyteno < &80 THENWait until R2DATA not full, write OSBYTNO(=&04) to R2DATAWait until R2DATA not full, write parameter for 65C12-X to R2DATAWait until R2DATA not full, write osbyte number to R2DATAWait for data in R2DATA, read R2DATA which is 65C12-X registerELSEIF osbyteno = &82 THENresult is machine high order addressELSEIF osbyteno = &83 THENresult is low memory valueELSEIF osbyteno = &84 THENresult is high memory valueELSEWait until R2DATA not full, write BYTENO (=&06) to R2DATAWait until R2DATA not full, write parameter for 65C12-X to R2DATAWait until R2DATA not full, write parameter for 65C12-Y to R2DATAWait until R2DATA not full, write osbyteno to R2DATAIF osbyteno=&9D THEN RETURN from protocol (no reply)(Note: this is why OSBYTE &9D is faster than OSBPUT)Wait for data in R2DATA, bit 7 of byte read is from 65C12-CWait for data in R2DATA, byte read is 65C12-YWait for data in R2DATA, byte read is 65C12-XOSWORDIF oswordno = &00 THEN [ (Note: Doing readline)Wait until R2DATA not full, write RDLNNO (=&0A) to R2DATAWait until R2DATA not full, write upper bound char to R2DATAWait until R2DATA not full, write lower bound char to R2DATAWait until R2DATA not full, write length allowed to R2DATAWait until R2DATA not full, write &07 to R2DATAWait until R2DATA not full, write &00 to R2DATAWait for data in R2DATA $ responseIF response > &7FTHEN [ ;escape was pressed on input RETURN from protocol ]Read a terminated string from R2DATA ]ELSE [ Wait until R2DATA not full, write WORDNO (=&08) to R2DATAWait until R2DATA not full, write oswordno to R2DATAWait until R2DATA not full, write number of params to send to R2DATAWrite parameter block to R2DATA, last byte firstWait until standard + tristateED6 13 I/O TTL standard + tristateED5 14 I/O TTL standard + tristateED4 15 I/O TTL standard + tristateED3 16 I/O TTL standard + tristateED2 17 I/O TTL standard + tristateED1 18 I/O TTL standard + tristateED0 19 I/O TTL standard + tristateCD7 28 I/O TTL standard + tristateCD6 27 I/O TTL standard + tristateCD5 26 I/O TTL standard + tristateCD4 25 I/O TTL standard + tristateCD3 24 I/O TTL standard + tristateCD2 23 I/O TTL standard + tristateCD1 22 I/O TTL standard + tristateCD0 21 I/O TTL standard + tristateBD7 40 I/O TTL standard + tristateBD6 39 I/O TTL standard + tristateBD5 38 I/O TTL standard + tristateBD4 37 I/O TTL standard + tristateBD3 36 I/O TTL standard + tristateBD2 35 I/O TTL standard + tristateBD1 34 I/O TTL standard + tristateVCC 30 Vcc connection (low inductance)GND1 10 Primary GND connection (low inductance)GND2 32 Secondary GND connection (low inductance)GND 3 20 Secondary GND connectionPAGE: 65AC Parametric Test Information - Timing SpecificationsTiming Point to point Parametric-Specification Time(ns) Output LoadSymbol measured at Vcc=Min Tamb=Max Min Max I/Face ValueTj1 M1 (LH/HL) jitter wrt M8 (HL) -30 +4Td1 EM1E (LH/HL) from M8 (HL) 0 60 TTL ATd2 ER/W (LH/HL) from RNW (LH/HL) 0 80 TTL ATd3 ER/W (LH/HL) from M8 (HL) 0 70 TTL ATd4 BR/W (LH/HL) from R/W (LH/HL) 0 50 TTL BTd5 CD7..0 stable data from NFIT (HL) 0 85 TTL CTe2 BD7..0 (ZH/ZL) from M8 (LH) 0 90 TTL BTz2 BD7. . 0 (HZ/LZ) from M8 (HL) 0 72 Z BTd6 B Bus , SA to SL data, from M8 (HL) 0 75 TTL BTd7 B Bus , SL to SA data, from M8 (LH) 0 90 TTL BTe3 ED7..0 (ZH/ZL) from NFIT (HL) 0 90 TTL ATz3 ED7. .0 (HZ/LZ) from M8 (HL) 0 105 Z ATz4 ED7..0 (HZ/LZ) from NFIT (LH) 0 105 Z ATd8 CD7. . 0 (LH/HL) from BD7 . .0 (LH/HL) 0 70 TTL CTd9 CD7. . 0 (LH/HL) from ED7. . 0 (LH/HL) 0 70 TTL CLoad circuit component values Load Value C(pf) R(ohms)For details of load circuit A 150 1000see AC measurement definition B 100 1000 C 170 1000Drawing not reproducedPAGE: 66SA data latching point.The video data for the SA5050 Teletext Display device is time divisionmultiplexed with the internal 1MHz peripheral data (as distinct from theexternal 1 MHz Bus). This data is latched at the point X in the timingillustrated below.Drawing not reproducedSL data latching pointData for 1 MHz internal peripherals is latched at the point Y on the timingdiagram below.Drawing not reproducedPAGE: 67C Bus Drive WaveformsThe peripheral bus controller drives the CPU data bus (the C Bus) on thefollowing occasions: a) Reading from internal peripherals b) Reading from the external 1MHz Bus c) Reading from the external TubeBecause these events may or may not be in phase with the CPU cycle, the PBC withholds the data until the correct time.Drawing not reproducedReading from the 1MHz Bus or an internal 1MHz peripheral. EM1E is in phase.Drawing not reproduced Reading from the 1MHz bus or an internal 1MHz peripheral. EM1E is early.Drawing not reproducedPAGE: 68B Bus Drive WaveformsThe B Bus contains both the internal 1 MHz peripheral data and the SAA5050video data. This bus is used by the Modem connector, so it IS important toobserve the timing constraints.Drawing not reproducedPAGE: 69E Bus Drive WaveformsThe E Bus operates at either 1MHz or 2MHz under the control of the CPU READYline, which it samples. This signal is driven by the 1/O controller with alogic low to slow the CPU down to 1 MHz when a slow access is made. The PBCextends its bus cycle time in much the same way as the CPU. In this way the1MHz Bus and Tube connectors can be driven by the same buffer. It is importantthat 1 MHz Bus peripherals using any significant length of ribbon cable(greater tha R2DATA not full, write number of parameters to receive to R2DATARead bytes back from R2DATA into parameter block, last byte first ]PAGE: 108The number of parameters to send/receive is determined by.IF oswordno < &14THEN [ Determine the number of parameters from following table:]OSWORD number Parameters to send Parameters to receive1 (&1 ) 0 52 (&2) 5 03 (&3) 0 54 (&4) 5 05 (&5) 2 56 (&6) 5 07 (&7) 8 08 (&8) 14 09 (&9) 4 51 0 (&A) 1 911 (&B) 1 512 (&C) 5 013 (&D) 0 814 (&E) 16 1615 (&F) 16 1616 (&10) 16 1317(&11) 13 118(&12) 0 12819(&13) 8 820 (&14) 128 128ELSE IF osword no < &80THEN Number of parameters to send=16Number of parameters to receive=16 ]ELSE[ Number of parameters determined in call specific manner (e.g. byembedding in transfer block)Wait until R2DATA not full, write parameters to send to R2DATAWait until R2DATA not full, write parameters to receive to R2DATAWait until R2DATA not fullTHEN [ Write parameter block via R2DATARead parameter block via R2DATA ]OSBPUTWait until R2DATA not full, write BPUTNO (=&10) to R2DATAWait until R2DATA not full, Y to R2DATA (file handle)Wait until R2DATA not full, A to R2DATA (byte to write)Wait for data from R2DATA, discard itPAGE: 109 OSBGETWait until R2DATA not full, write BGETNO (=&0E) to R2DATAWait until R2DATA not full, write file handle to R2DATAWait for data in R2DATA, top bit of byte is 65C12-C (validity bit)Wait for data in R2DATA, read R2DATA which is byte read from file.OSFINDWait until R2DATA not full, write FINDNO(=&12) to R2DATAWait until R2DATA not full, write type of open to R2DATAIF type=0THEN [ Wait until R2DATA not full, write file handle to R2DATAWait for data in R2DATA, Read result ]ELSE [ Wait until R2DATA not full, write file name string to R2DATA(including terminating )Wait for data in R2DATA, read handle from R2DATA ]OSARGSWait until R2DATA not full, write ARGSNO (=&0C) to R2DATAWait until R2DATA not full, write file handle to R2DATAWaiting for R2DATA not full, [write 4 bytes osarg-data to R2DATA (mostsignificant byte first)Wait until R2DATA not full, write operation code to R2DATAWait for data in R2DATA, read fs type from R2DATAWaiting for R2DATA , read 4 bytes osarg-data from R2DATA (msb first) ]Note: osarg-data is the file sequential pointer or length depending on thetype ofOSARGS call.OSFILEWait until R2DATA not full, write FILENO (=&14) to R2DATAWaiting for R2DATA not full, [write 16-byte OSFILE control block to R2DATA](last byte of block is written first)Waiting for R2DATA not full, write filename to R2DATA including Wait until R2DATA not full, write type of transfer to R2DATA (Any transfer iscompleted under interrupt using R3, R4)Wait for data in R2DATA, read R2DATA AND &7F = Filing system typeWaiting for data in R2DATA, [read back 16-byte control block from R2DATA ](last byte of block is read first)Note: The 16-byte control block has the format:0 Load address * The contents of these4 Execution address fields depend on the call8 Data start address or Length* type e.g. catalogue12 End address or attributes information, file addresses. See the Reference Manual, Part 1.PAGE: 110OSGBPBWait until R2DATA not full, write GBPBNO (=&16) to R2DATAWait until R2DATA not full, [write 13-byte OSGBPB control block toR2DATA ] (last byte of block is written first)Wait until R2DATA not full, write type of transfer to R2DATAWaiting for data in R2DATA, [read back 13-byte control block from R2DATA(last byte of block is read first)Wait for data in R2DATA, read R2DATA bit 7 is 65C12-C bitWaiting for data in R2DATA, read 65C12-A from R2DATAInterrupt driven operationsIn addition to these parasite-initiated activities the parasite is alsorequired to respond to interrupts from registers 1 , 3 and 4.To determine the source of an interrupt it is important to follow thefollowing order.a) Check for register 4 interruptb) Check for register 1 interruptRegister 1 interruptsRegin 30cm) use 2k pull up/down resistors to minimise line reflectionsto the Tube.Drawing not reproducedCase 1 - Writing to the tube.Drawing not reproducedCase 2 Writing to the 1MHz BusBoth of the two possible timing relationships are shown. The data has a nominal250ns data setup time before the rising edge and a minimum hold time of 125nsafter the falling edge of EM1E (measured at the PBC). The address set up isalso shown. This is generated by a latch clocked at 4MHz and so presents aminimum address set up time of 250ns and a minimum address hold time of 250ns.Drawing not reproducedPAGE: 7018 THE 1MHz BUSThis chapter describes the signals available on the 1 MHz Bus, the circuitryrequired to utilise them, and the way in which they are connected to the AcornExpansion Box. The expansion memory map is also defined. When interfacingdesigns to the 1 MHz Bus, it is vital to ensure compatibility with Acornstandards, to prevent problems when using several pieces of equipment on thebus simultaneously.The standards cover both hardware and software protocols. It is as importantfor the software to follow these guidelines as it is for the hardware,otherwise simultaneous operations of several peripherals may not be possible.The standards described allow up to 64K of paged address space to be accessedas well as 255 bytes of direct access ports.Signal definitionsThe following lines are available on the 1 MHz Expansion Connector.A0-A7 The low eight address lines from the 6502, buffered by a74LS244 (IC 71) permanently enabled.DO- D7 A bi-directional data bus connected to the CPU throughIC 72, a 74LS245 buffer. The direction of data isdetermined by the system Read-not-write (R/W ) line. Thebuffer is only enabled if nPGFC or n PGFD is low (seebelow).Analogue in An input to the BBC Microcomputer audio circuitry. Inputimpedance is 9K. A signal of 3volts RMS will produce asaturated signal at the loudspeaker (full volume), thoughsignals this large will cause distortion if the on-board soundor speech is used at the same time.nRST Not Reset. This is an OUTPUT ONLY for the system resetline (active low). It may be used to initialise peripherals onpower-up and when the 'BREAK' key is pressed.nPGFC & nPGFD 'Not page FC' and 'Not page FD'. Page select signalsdecoded from the top eight address bits of the system databus. These signals are active low. Pages FC and FD (i.e.&FC00 to &FCFF and &FD00 to &FDFF) are the onlypages available for general expansion. However, thePAGE: 71paging register described in Section 5 allows a muchlarger address space to be accessed.nIRQ Not Interrupt Request (active low). The system IRQ linewhich is open collector (i.e. 'wired-or') and may beasserted by devices attached to the extension bus. Thepull-up resistor on this line is 3K3. 1 RQ is level triggeredand it is absolutely essential for correct operation of themachine that interrupts do not occur until the software iscapable of dealing with them. Interrupts on the 1MHz busshould therefore be disabled on power-up and resetconditions. Significant use of interrupt service time mayaffect other machine functions. In particular, maskinginterrupts for more than 1 OmS will affect the real timeclock.nNMI Not Non-Maskable Interrupt (active low). The system NMIline which is open collector (i.e.'wired-on') and may beasserted by devices attached to the extension bus. Thepull-up resistor on this line is also 3K3. It should beremembered that NMI is negative-edge triggered and thatboth the disc and net chips on the main board use this line.Caution must be exercised to avoid masking otherinterrupts by holding the line low. Use of NMI facilities onthe BBC machine requires an advanced knowledge of65O2 programming techniques and the Operating SystemProtocols.1 MHzE A system clock timing signal which is a 1 MHz 5O7% duty-cycle square wave. During access to 1 MHz peripheralsand to the extension bus the processor clock (normally2MHz) is stretched so that the trailing edges of 1MHzE andprocessorster 1 interrupts occur only in the host-to-parasite direction. Theinterrupt service sequence is:Read type byte from R1DATAIF type < 0THEN [ . Escape flag updateReplace the escape flag with bit 6 or typeRETURN from servicing interruptELSE Event signalInterrupt-R1 DATA-read 65C12 Y-event parameterInterrupt-R1 DATA-read 65C12 X-event parameterInterrupt-R1 DATA-read 65C12 A-event parameter; Host machine will now continue processing; any other actions to service event can be taken ]Where Interrupt-R1 -read is:UNTIL data-ready-in-R1DO IF data-ready-in-R4 THEN CALL R4-interrupt-service ]RETURN read R1DATAPAGE: 111Register 4 InterruptsRead Type byte from R4DAT AIF TYPE < 0THEN ; HOST machine is reporting an errorWait for data in R2DATA, read and discard itWait for data in R2DATA, Read error number from R2DATARead a zero byte terminated string from R2DATA ]Else[;.Type is a command to initialise for Register 3 block transferWait for data in register 4, read claimer's identity from R4DATA (See Note 4)CASE Type OF0 - Single byte transfer Parasite to Host.Read 4-byte base address for transfer from R4DAT A msb first.Set NMI routine for this transfer type.Wait for & remove synchronising byte from R4DATA ]1 - Single byte transfer Host to Parasite.Read 4-byte base address for transfer from R4DAT A msb first.Set NMl routine for this transfer type.Wait for & remove synchronising byte from R4DAT A2 - Double byte transfer Parasite to Host.Read 4-byte base address for transfer from R4DATA msb first.Set NMI routine for this transfer type.Wait for and remove synchronising byte from R4DAT A3 - double byte transfer Host to Parasite.Read 4-byte base address for transfer from R4DAT A msb first.Set NMI routine for this transfer type.Wait for & remove synchronising byte from R4DATA4 - No transfer ( Pass address Host to Parasite only ).Read 4-byte address from R4DAT A msb first.Wait for data in R4DATA, discard it.5 - No transfer ( Filing system release )6 - 256-byte transfer Parasite to Host without interrupt.Read 4-byte base address for transfer from R4DAT A msb first.Wait for data in Register 4, discard it.Transfer 256 bytes to Host via R3DATA.Write a byte into R4DAT A .To stop unwanted interrupts on Host7 - 256-byte transfer Host to Parasite without interrupt.Read 4-byte base address for transfer from R4DAT A msb first.Wait for data in Register 4 , discard it. Transfer 256 bytes from Host viaR3DATA.] RETURN ; From the interruptPAGE: 112Notes:1 ) Synchronising Bytes for types 0-3. As soon as the synchronising byte isremoved, Register 3 transfer requests (NMls) will start to occur. The data in asynchronising byte has no meaning; it is merely a handshake signal. When theinterrupt occurs 1 or 2 bytes are transferred (depending on the current mode).2) Filing System releases NMI ownership. A release (type 5) is a guaranteethat no more Register 3 NMls will occur for the current transfer.3) Interrupt Service Time. The interrupts are caused by some externalperipheral (e.g. discs or the ECONET) which cannot be slowed down, so thetransfers must take place within the following times: Type Maximum allowed Time for Maximum permissible service time NMI service routine from sync byte to first transfer NMI0 24 ms per byte 24 ms1 24 ms per byte 24ms2 26 ms per pair of bytes 24ms3 26 ms per pair of bytes 24ms6 10 ms per byte 19 ms7 10 ms per byte 19 ms4) Filing System claimer identitiesWhen a filing system claims the R3/R4 resource in the Host its identity ispassed to the second processor as part of the R4 startup protocol. The identitycodes, which are six-bit numbers, are not related to filing system or ROM slotnumbers. They are arbitrary assignments made by ACORN.Filing System Claim identity usedTape 0DFS 1NFS (Low Level) 2NFS (Filing System) 3ADFS 4TFS (Telesoft Filing System) 5Reserved for Acorn Use 6VFS (Video filing system) 7SRM (SRAM Utilities) 8Z80 (For CP/M usage) 9The Identity '&F' has been used by an inde clock are coincident.R/W The system Read-Not-Write signal which is derived fromthe CPU R/W signal through two 74LSO4 inverters..0V System OV, i.e. GND wires, dispersed so as to interleavewith asynchronous groups of signals in a flat ribbon cable.PAGE: 72Hardware requirements for1 MHz expansion bus peripheralsNo power may be drawn from the BBC Microcomputer. Each peripheral shouldhave its own integral power supply, although a separate power unit may be used.Not more than one low-power Schottky TTL load may be presented to any bus lineby each peripheral.A 1 MHz Bus feed-through connector should be provided. Connection to the BBCMicrocomputer should be via 600mm of 34-way ribbon cable terminated with a 34-way IDC socket, and fitted with strain relief. Please note that copying theTeletext Adapter's layout is not possible, because this has been given thespecial status of the last box in the chain.Optional bus termination should be provided on all bus lines except NRST , NNMIand NIRQ. The recommended termination is a 2K2 resistor to +5V and a 2K2resistor to ground for each line.Further requirements for equipment to be approved by Acorn ComputersAddress space within page &FC must be allocated by the Research andDevelopment Department of Acorn Computers Ltd.The dimensions of any peripheral and its associated integral power suppliesshould allow it to be fitted into the BBC Microcomputer Expansion Box.When housed in the Expansion Box, the equipment should meet BS415 Class 1specifications for electrical safety.Further details of the requirements and procedures for gaining approval shouldbe obtained from Acorn. The information included here is for guidance only andis not intended to be a full specification for approval.PAGE: 73Derivation of valid Page signals1MHz peripherals are clocked by a 1 MHz 50070 duty cycle square wave (chosen toallow chips such as the 6522 to use their timing elements reliably). The MasterSeries 65C12 normally operates with a 2MHz clock, but with a slow-down circuitwhich has the effect of stretching the 'clock high' period immediatelyfollowing the detection of a valid 1 MHz peripheral address.There are two problems as a result of this. First addresses will change and maymomentarily become 1MHz addresses while the 2MHz CPU clock is low, but whilethe 1 MHzE signal is high. This could give rise to a spurious pulse on the chipselect. Second, if the CPU deliberately addresses a 1 MHz peripheral during thetime that 1 MHzE is high, the device will be addressed immediately, and thenagain when 1 MHzE is next high: this is because the CPU clock will be held'high' by the stretching circuit until the next coincident falling edge of the1 MHz and 2MHz clocks. This double access is not usually a problem except whenreading from or writing to a location twice has some additional effect: anexample of this is an interrupt flag which is cleared by reading it.These effects mean that the 1 MHzE Bus cannot be used as a conventional'address valid' signal. However, addresses will always be valid on the risingedge of 1 MHzE. If the chip select lines are latched by 1 MHzE, the cleansignal CNGFC (or CNPGFD) will be generated.Address space allocationPage FCPage FC is reserved for peripherals with small memory requirements. Only oneperipheral will be allocated to each group of addresses. Further allocationsmust be agreed with the R & D department of Acorn Computers Ltd.Initial allocations are:FC00 to FC0F Test HardwareFC10 to FC13 TeletextFC14 to FC1 F PrestelFC20 to FC27 IEEE 488 InterfaceFC28 to FC2F Acorn Expansion: spareFC30 to FC3F Cambridge Ring InterfaceFC40 to FC47 Winchester Disc InterfaceFC48 to FC7F Acorn Expansion : spareFC80 to FC8F Test HardwarePAGE: 74FC90 to FCBF Acorn Expansion: spareFCC0 to FCFE User ApplicationsFCFF Paging RegisterPage FDPage FD is used in conjunction with the paging register to provide a 64Kaddress space, accessed one page at a time. Each BBC Expansion Box will have apaging register on the back pendent manufacturer.PAGE: 113Startup protocolThe startup sequence for a language processor (e.g. when power is switched on,or Reset is pressed) is:Use the OSWRCH mechanism to write out a startup message.Send a zero byte to Host via R1 DATA to terminate it.Wait for data in R2DATA. ; during this wait a load may occur from the Host ; using R4/R3 block transfer protocolsIF byte=&80 THEN execute from the address given in the R4 type 4 transfer.Notes:1) The host operates the Tube by polling the registers, i.e. not by interrupts.2) In all the transactions which may generate errors it is important torealise that if the error is reported by the BBC machine under interrupt(i.e. it was generated by a 65C12 BRK sequence), the protocol which generatedthe error is abandoned.Register AddressesThe Tube can be put anywhere in the parasite memory map that is convenient tothe language processor designer. In the 65C102 Co-processor and 6502 SecondProcessor, for example.Register Address in Parasite memory mapR1STATUS &FEF8R1 DATA &FEF9R2STATUS &FEFAR2DATA &FEFBR3STATUS &FEFCR3DATA &FEFDR4STATUS &FEFER4DATA &FEFFTube protocolsHost ProtocolsThe host protocols obtain or distribute data which the parasite has requestedortransmitted. Normally it is the MOS which responds, as the majority of OSBYTEand OSWORD calls are concerned with accessing hardware or flow controlparameters stored in RAM. However, when data has to be passed quickly or inbulk, this is usually done by filing systems working under NMIs. The user hasPAGE: 114access to the same facilities as filing systems (via Register sets 3 and 4)and can load a program into the host which may take advantage of these.The procedure has five phases:1) Check that the Tube is present2) Claim the Tube3) Initiate the data transfer4) Transfer data5) Release the TubeCheck for presence of the TubeAs a file intended for a parasite may be loaded into the host when the Tube isnot present, it is a good practice to check for the presence of the Tube bycalling OSBYTE 234 (&EA) with X=0, Y=255. On return, X=0 if the Tube is notpresent, otherwise X=255.Claiming the TubeFor the user to gain control of the Tube permission is requested by callingthe MOS Tube entry point at &0406 with a unique 'reason code' in the 65C12accumulator. The reason code is a six-bit number logically ORed with &C0, thussetting the top two bits. For example, (in BBC BASIC assembler) :reason% LDA #(&C0 OR ) The Accumulator now holds the reason codeThe already in use are listed above. For third partysoftware writers, they are allocated by Acorn Customers Services to preventclashes with other proprietary software.When the call returns, the CPU carry bit will indicate if the call wassuccessful or not: C=1 : The call was successful C=0 . The call failedIf the call failed, this is because some other program had control of theTube. The call should be repeated until successful:reason% JSR &0406 ;Call Tube code BCC reason% ;Try to claim the Tube ;try again if failed RTSRegisters (A, X, Y as appropriate) should be saved as they may be corrupted onreturn.PAGE: 115Initiating data transferOnce the Tube has been successfully claimed, a control block must be set up inthe host indicating the address of the first byte in the target area in theparasite. This in its turn is pointed at by loading the CPU's X and Yregisters with the high byte and low byte respectively of the control block'saddress: n+3 Target address high byte n+2 Target address high byte-1 n+1 Target address low byte +1 A n Target address low byte (Y*&100 + X)When the control block is set up, the same entry point (&0406) is used toinitiate data transfer. Once again a reason code in the accumulator is used,this time to indicate what action is required:Reason code Description Delay(a) Delay(b)0 Multiple byte transfer PÞH 24ms 24ms/byte1 Multiple byte transfer HÞP 0 24ms/byteThese transfer any number of plane, thus data will be latched simultaneously Onevery Expansion Box. Data latched into the paging register will provide thetop eight address bits to the Eurocard back plane. These top address bits arereferred to as the 'Extended Page Number'. Any peripheral designed to locatein page FD without using an expansion back plane must latch and decode thepaging address information.To make this facility as easy to use as possible, nPGFD (a hazard-free versionof the signal available from PL12) will be connected to the back plane pin 24b,'Not Valid Memory Address' , and also OR-ed with the top four extended pageaddress lines as a link selectable option to pin 31a 'BLKO'. (the other optionon this pin will be n PGFC).Extended pages &00 to &7F are reserved for Acorn use, pages &80 to &FF may befreely used by special applications. The paging register will be reset to &00on power-up and BREAK.Since the paging register is a write-only latch, location &00EE in the zeropage of the BBC machine address map has been allocated as a RAM image of theregister. Note that this location will remain in the l/O processor's memorymap if a second processor is fitted.The importance of this image is that it allows interrupt routines to changethe paging register and restore it again afterwards.It is vital to change location &00EE BEFORE changing the paging registeritself. If you don't, then an interrupt may occur before you change the RAMimage and this will restore the paging register to the old value of &EE.A suitable sequence isLDA # new valueSTA &EESTA &FCFFUser routines should save the contents of &EE before changing the pagingregister and restore both &EE and &FCFF to this value before returning from theinterrupt.PAGE: 75Drawing not reproducedTiming requirementsParameter Symbol Min. Max.Address Set-up time t as 300 1000(& R/W Set-up time)Address Hold Time tah 30(& R/W Hold Time)NPGFC & NPGFD Set-up Time tcs 250 1000NPGFC & NPGFD Hold Time tch 30Write Data Set-up Time t dsw 150Write Data Hold Time t dhw 50Read Data Set-up Time t dsr 200Read Data Hold Time t dhr 30Note: The above timings are based on only one peripheral attached to theExpansion Bus. Heavy loading may slow the rise and fall times of 1 MHzE withpossible adverse effects on timings.PAGE: 76R-S flip-flop with gated input which allows 'clean select' to be set low onlyif 1 MHzE is low. An alternative circuit using transparent flip-flops isshown on the circuit diagram for the Expansion Box back plane (Drawing107,000,)PAGE: 7711 THE MACHINEOPERATING SYSTEMThis section explains how to extend the MOS facilities of the microcomputer,such as the VDU driver and the TUBE interface. It includes a full address map(which has indicators showing where the MASTER 128 and the MASTER EconetTerminal differ from the earlier BBC machines), the vector allocations (whichare given in full) and details on the use of vectors with interrupts and theTube. It may be helpful to refer to the chapter on the MOS in Part 1 of theReference Manual for additional information.Address spacemapThe address space map, which shows the address allocations and the areas ofmemory used by the computer, indicates to a programmer which areas of thememory are available for him to use. However , it does not show individualinput/output allocations as they have already been documented in Part 1 of theReference Manual.Although this section explains how to use areas of memory which are normallyreserved for specific purposes, Acorn does not condone the practice, as it maylead to software incompatibility when used on a machine other than the one onwhich it was written or if the configuration of the machine is changed.Page0&0000-&008F. current language workspace - some languages e.g. BASIC, allowother programs to use areas of free memory,&0090-&009F. ECONET private workspace - not available for any other use.&00A0-&00A7. Non-Maskable Interrupts (NMl) workspace - may be used onlyafter NMI has been claimed. Thbytes. Terminate by releasing the Tube or startinganother protocol.2 Multiple pairs of bytes PÞH 26ms 26ms/pair3 Multiple pairs of bytes HÞP 0 26ms/pairThese transfer an even number of bytes and are faster than the above twoprotocols as they use R3DATA in its two byte mode. Terminate by releasing theTube or starting another protocol.4 ExecuteExecution starts at the address pointed to by the control block (see below).This option has an implied release of the Tube and does not return to theuser's program.5 ReservedThis option is used in handling MOS calls which are passed across the Tube.6 256-byte transfer, PÞH 19ms 17 256-transfer, HÞP 0 10ms/byteThese will transfer exactly 256 bytes. Only after completion can the Tube bereleased or another protocol started.Note that the reason codes and functions are the same as the parasite sideR4DATA transfers.PAGE: 116Transferring dataAfter the instruction has been passed to the system, the user program canstart the transfer after the delay specified above. In the P-H direction thedelay (a) allows the parasite CPU to service the initiating NMI and 'prepareitself' before the data starts. In the HÞP direction this will already havebeen done as it would have been the parasite which issued the call asking thehost to fetch the data. Once transfer has started, the delay (b) must beallowed between bytes (or pairs of bytes as indicated above) to allowsufficient time for the parasite R3DATA NMI code to complete. In the ps-Hdirection, the host must service each byte (or pair) within the indicated time.Releasing the TubeWhen the transfer is complete, the Tube must be released so that anotherprogram can use it. The procedure is to call the MOS Tube entry point, againwith a reason code in the accumulator , this time using:release% LDA #(&80 OR ) JSR &0406 RTSOnce again, CPU registers must be saved as appropriate.Register LocationsThe Tube registers have the following locations in host memory map:Register LocationR1STATUS &FEE0R1DATA &FEE1R2STATUS &FEE2R2DATA &FEE3R3STATUS &FEE4R3DATA &FEE5R4STATUS &FEE6R4DATA &FEE7In practice, R3DATA is the register of prime interest as this is the datachannel for the transfers described above, that is:A HÞP transfer : LDA data-source STA R3DATAPAGE: 117A PÞH transfer: LDA R3DATA STA safe-placeTube/filing system interfacePart 1 of the Reference Manual describes in some detail the format of thefiling system interface (OSFILE, OSARGS etc.). The following information isintended to assist in the writing of filing systems which must be compatiblewith the Tube.LOAD/SAVE addressesIt is necessary to indicate to a filing system whether a file's target addressis in the host or the parasite address space. This is done by treating theaddress as a four- byte (32-bit) number where the two most significant bytesindicate the relevant side of the Tube:&FFFF indicates the host memory WARNING When the Tube is active, its communications code is in &FFFF0400 to &FFFF07FF&FFFFFFFF indicates that the named program is to be EXECed&FFFE<3000 to 7FFF> indicates the 'shadow' screen memory in the host This does not apply to CFS, TFS and RFS.&JKLM<0 to FFFF> indicates the parasite memoryThis means that parasites can have memory from &00000000 to &BFFFFFFF. Fora program in the parasite to set up a utility program (say, an interrupthandler), it should do either of the following:Using OSWORD1 ) Transfer a small routine to disable interrupts, then modify theinterrupt vector and re-enable interrupts.Using *RUN1 ) Issue a *RUN FFFF.In this case, the utility will be loaded and JuMPed into at the entry pointstored on the filing media (e.g. disc). The utility should then :-2) Modify the relevant vector itself to point to the 'real' entry point andthen do an RTS to cause the parasite protocol to be terminated.PAGEe source of the NMI has a filingsystem number allocated to it (rather than a ROM number) and itmust be able to service the calls &0B and &0C (which indicatesthat it is either in the 'sideways' region &8000 to &BFFF, or that itcan intercept OSBYTE &8F). NMls should not change anylocations unless they are specifically allowed to or unless it istheir own workspace.PAGE: 79&00A8-&00AF MOS scratch space. It is not necessary for this space to bepreserved between MOS system calls and therefore may be usedby other programs during this time. However, it is notrecommended for general use because the integrity of the spacewill not be preserved across MOS calls.&00B0-&00BF filing system scratch space - like the MOS scratch space it is notpreserved between system calls. During this time other programsmay use it although this practice is not recommended becausethey will not be preserved across filing system calls. 'Hidden'filing system calls e.g. those produced by OSWRCH if thecommand *SPOOL has been used also use this space.&00C0-&00CF current filing system workspace - under no circumstances mustthis area be used because it may be corrupted at any time&00D0-&00FF MOS workspace - not available for use by other programs. TheVDU driver is fully explained in section E of Part 1 of theReference Manual,In previous BBC microcomputers this area contained variouspointers and flags for 1/O operations. This is not the case with theMaster Series.Pages 1 to &D&0100-&01FF processor stack and error messages buffer. The stack followsnormal 6502 practice and works as a LIFO buffer at the top of thepage. Error messages are stored temporarily at the bottom of thepage.&0200-&0235: vector addresses. For more details of this area please refer tothe section on Extending the MOS.&0236-&028F. main MOS variables - not recommended for any other purpose.&0290-&02FF . MOS workspace - not available for other purposes.&0300-&037F. VDU variables. It is only possible to us this area for graphicsroutines, more details on the use of these are available insections D, E and F of the Reference Manual Part 1 . In earlierBBC microcomputers some of the variables had differentfunctions, details of which are given in the Appendices.PAGE: 80&0380-&03DF Cassette Filing System workspace - available only if the CFS isnot used.&03E0-&03FF keyboard input buffer - available only if the keyboard buffer hasbeen replaced.&0400-&07FFlanguage workspace - may be used if the current languageallows (e.g. BASIC ). It is also used for the relocation of the hostcommunications routines with second processors.&0800-&087F sound workspace - its use is not recommended as this maycause the generation of spurious sounds.&0880-&08BF printer buffer - may be used for other purposes if printing is notrequired.&08C0-&08FF workspace for the sound envelopes 1 to 4 - available for otherpurposes if the envelopes are not used.&0900-&09BF RS423 output buffer, cassette output buffer for access to the firstpart of sequential files or workspace for sound envelopes 5 to 16- otherwise available for other purposes.&09C0-&09FF Speech buffer or cassette output buffer for access to the secondpart of sequential files - available to users if not required for thesepurposes.&0A00-&0AFF RS423 input buffer or the cassette input buffer for access tosequential files - available for other uses if not required for thesepurposes.&0B00-&0CFF. ECONET workspace - may not be used for any other purpose ifat any time the computer will be connected to an ECONETsystem. In previous BBC microcomputers this area was used forthe soft key buffer and the upper 32 characters of the explodedfont. This means that previous routines for writing a soft keydefinition directly into the memory can no longer be used.Correct operation on the Master Series and on the earlier BBCmachines can be achieved by using the OSCLI interlace.&0D00-&0D5F. NMI routine workspace. In order to make use of this area forother uses NMls must be claimed (paged ROM service call: 118Use of the Non-Maskable InterruptTo avoid slowing the computer down with polling loops, programs which have tointerface at high speed with the real world use interrupts. The MOS providesand maintains a flexible and powerful 1 RQ-based 'event' structure. Anyprogram, be it in RAM, sideways ROM or sideways RAM can couple to thisstructure by purpose- designed OSBYTE calls and vector redirection.The penalty for this flexibility is the time it takes to let all interestedparties know that an IRQ has happened. Usually this is not important. However,where a filing system is reading floppy discs, for example, there isinsufficient time to call a routine in the MOS and then let it tell all theother systems until it eventually reaches the filing system. For this reasonthe Non-Maskable Interrupt (NMI) is used for critical data transfers.To ensure that the NMI is serviced quickly enough, the MOS exercises no controlover it. Not even a vector is used as its redirection would take 2ms. Todistribute this valuable resource, the MOS maintains an arbitration system toensure that only one program at a time is trying to use the NMI.Claiming NMI workspace(&0D00 to &0D5F and &00A0 to &00A7)Even if an IRQ and NMI are made to the CPU at exactly the same time, the NMIwill take priority. The CPU will JMP via an address stored at a fixed locationin ROM to the start of a region in RAM which is reserved for use as NMIWorkspace. When the computer is reset, this location is loaded with an RTI sothat spurious interrupts will not cause the computer to 'crash'. For a programto make use of NMIs, it must put a short routine into memory from &0D00. Thisshould:a) Do the minimum to ensure integrity of the previous routine (i.e. savingregisters on the stack).b) Service the interrupt as efficiently as possible.c) ReturnIt is important that programs do not try to use the NMI workspace before theMOS has given permission for this. Otherwise it could interfere with anotherprogram (such as a filing system) which was already using NMIs.The NMI workspace and hence NMls are claimed as follows:a) Issue a service request to claim the NMI (OSBYTE 143 (&8F); X=&0C).b) When the service request comes round, any NMI owner should 'switch off'its NMI usage. NMIs will be allocated to another program. This call must notbe claimed, but passed on to the next sideways program. On return, the Yregister should be saved as it will contain the identity of the previous owner.This call should only be issued if the current owner is the Network software orPAGE: 119none at all. If it is issued whilst ADFS (or DFS) is active, data or evendirectories may be lost.When the NMls are no longer needed, they should be released thus:a) Issue a service request to release the NMI (OSBYTE 143 , X=&0B,Y=)NMIs should be released by synchronous systems (such as the disc interfaces)when a given task is complete. It will then be claimed by an asynchronoussystem (such as the Network) until such time as it is needed again by asynchronous one.Hardware access to the NMIThe following interfaces have a connection to the NMI signal:1 ) Disc interface2) Econet adapter3) 1 MHz Bus4) The Cartridges5) The Modem CavityThe disc and net interfaces are not directly connected to the CPU NMI-pin forthe following reasons:The Disc InterfaceThe WD1770 series disc controllers have two interrupting outputs. Oneindicates that a new byte has to be read from/written to the disc; the otherindicates that the last command has been completed. Both of these signalshave active high totem pole outputs whilst the system uses an open collector,active low system. The two interrupts are logically open collector NORed inthe 1/O controller.Note that some machines are fitted with the WD1772 in place of the WD1770.The Network AdapterThis uses a 68B54 Advanced Data Link Controller and will generate aninterrupt for every data byte assembled from the ECONET. As net trafficmay be generated by other users, it is desirable to prevent the 68B54from &0C) . The same restrictions apply to the use of this area as to&00A0-&00A7 which is described above. On earlier BBCmicrocomputers this region extended to &0D9E.PAGE: 81&0D60-&0D7F ECONET workspace - it may be used for other purposes if themachine is not going to be connected to an ECONET system.&0D80-&0D91 : available for user programs.&0D92-&0D9E: Reserved for a Trackerball or Mouse. It is necessary for thesedevices to have immediate access to non-paged memory in orderto service the interrupts from their reference phase signals. Thisarea has been reserved for fast updating of their counters.&0D9F-&0DEF extended vector address set, more details of which can be foundin the section on extending the MOS.&0DF0-&0DFF paged ROM workspace. Usually one byte for each ROM is usedfor the high byte of the private workspace address. Some ROMs,such as the DNFS also use it to indicate that they are not activeby resetting bit 7. The reason for the inactivity may be, forexample, that essential hardware is not present or that aparticular filing system is dormant.Pages &E to &7FThe allocation of this area of the memory is variable. Some of the pages at thelower addresses may be used by the paged ROMs or by programs that raise theOperating System High Water Mark (OSHWM). Some pages at the higheraddresses may be allocated to the screen, if it is not in shadow mode. Theremaining memory is allocated to user memory, i.e. language workspace.In the Master Series soft character definitions are held in RAM at &8000,whereas earlier BBC microcomputers stored them in RAM above &0E00, raisingOSHWM.Pages &80 to &BFAt any one time, one of sixteen images resides in the memory pages &80 to &BF.These images may be in ROM, RAM, or EPROM and include parts of the operatingsystem, the sideways MOS ROM (ROM &F and the top 1.5k of the ROM &E).The MOS makes the paged ROM code in the address range &8000 to &8FFFunavailable during graphics and soft-key calls by setting the high bit of theROMselect latch high. This swaps in 4k from a further 32k of RAM. Paged ROMS whichneed to use of this area can do so by calling routines given in the VDU driversspecification section of Part 1 of the Reference Manual. Note great care mustbetaken when laying out these ROMS to avoid attempts to execute ROM code withinthe overlaid area.PAGE: 82Sideways ROM numbers 0,1,2 and 3 are allocated to the cartridges and a further'vertical' paging mechanism may be used with these. When using the 'vertical'paging mechanism some 1Mbit and 512kbit EPROMS are arranged as sixteen andeight pages of 16k bits respectively. When these devices are plugged into thecartridge slots they will appear as a 16k byte image, but any one of theremaining seven (for the 1 Mbit) or three (for the 512kbit) images may beobtained by writing to the EPROM with the vertical page number. This a majordeparture from standard EPROMS and allows 512k bytes to be fitted into fourEPROMS and yet only use 16k of the computer's address space. This isillustrated below.To insert the paged EPROM into the memory map of the computer the value of theEPROM is written to address &FE30. The required vertical image is then selectedby writing to any location in the range &8000 to &BFFF. Note this selection ismaintained even if through a hard break (e.g. CTRL-BREAK). The next access tothese sideways EPROMS will be from the new image. On power-up the specialEPROMS default to vertical page 0. To use this facility include a standard ROMheader line for each vertical page. An example of a typical paged EPROM is the27513, which is four pages of 16k bytes.PAGE: 83Pages &C0 to &DF and page &FFThe main MOS ROM resides in the areas &C0 to &DF and &FF However, in thestandard configuration pages &C0 to &DF of the MOS are not directly readable,because the filing system RAM is switched into this area. This part of the MOScontains the graphics routines and is enabled when needed. Another featurewhich should be noted is that access by instructions in the area &C0 to &DF togenerating NMIs when the ANFS is not the NMI owner. As the68B54 does not have an interrupt mask, logic, again in the I/Ocontroller, performs this function.Suggestions of uses for NMls other than the disc and net interlaces are .Infra-red data transfer cartridge, for example, fibre opticCompact Disc filing systems (CD- ROMs)Video Disc filing systems, for example, BBC Domesday ProjectHigh speed modemsPAGE: 12013 THE Z80 SECONDPROCESSOROperating system callsThe operating system calls of the host processor can be accessed from the Z80in asimilar manner to the BBC Microcomputer itself. Operating system calls can bemade via a jump table starting at address FFCEh. The entry point for eachroutine corresponds with the equivalent address on the 6502, e.g. the WRCHroutine is entered at FFEEh. All operating system calls (apart from OSARGS -see below) take parameters in Z80 registers A, H and L corresponding to A, Yand X on the 6502. For all calls that use the carry flag on the 6502 thisstill applies on the Z80. For example:LD A,41h ;Character to be written in ACALL 0FFEEh ;Call OSWRCH to write characterandLD A,5 ;*FX 5,2 => A set to 5LD L,2 ;L set to 2CALL 0FFF4h ;Call OSBYTE routine equivalent to *FX 5,2Interception of any operating system call can be achieved by simply changingthe address field of the relevant jump to point to the required user routine.The new memory map is shown belowAddress (Hex) Purpose FFFE I NT vector reserved for the Z80 operating system FFFC Event vector FFFA BRK vector FFF7 OSCLI- H,L point to command line FFF4 OSBYTE - A = OSBYTE number H,L are parameters FFF1 OSWORD - A = OSWORD number H,L point to control block FFEE OSWRCH - A = character FFE7 OSNEWL - Write linefeed, carriage return to screen FFE3 OSASCI - Write character in A to screen plus line feed ifPAGE: 121FFE0 OSRDCH - A = characterFFDD OSFILE - A = Operation type H , L point to control blockFFDA OSARGS - A = Operation type E = Handle H,L point to control blockFFD7 OSBGET - A = Byte H = File handleFFD4 OSBPUT - A = Byte H = File handleFFD1 OSGBPB - A = Operation type H,L point to control blockFFCE OSFIND - A = Operation type H , L point to filename (A0) H = file handle (A=0)FFC8 TERM - A=0 Switch off terminal mode (default), A=1 Switch on terminal mode, A=FFh Test terminal modeFF82 Fault pointerFF80 Escape flag - top bit set if escape condition existsFaults and events6502 FaultsWhen a fault is generated by the 6502 host processor the Z80 is interruptedand the fault number and string are passed across the Tube and placed in anfault buffer.The pointer at FF82h is then set to point to the fault number and the Z80operating system indirects through the BRK vector at FFFAh.Z80 FaultsFaults can also be generated on the Z80 using the RST 38h instruction. All Z80-generated faults should adhere to the following convention:RST 38h Value FFhFault numberFault stringTerminator Value 00hEventsWhen an event is detected by the 6502 operating system the event parameters A,Y and X are passed across the Tube to Z80 registers A, H and L respectively.The Z80 operating system then indirects through the event vector at FFFChwhich is initialised to point to a Z80 RET instruction.PAGE: 122Escape processingWhen the escape code is detected from the keyboard the top bit of the escapeflag at FF80h is set. An escape condition should be detected by testing thisbit and acknowledged by OSBYTE call 7Eh. The escape flag should be reset orset using OSBYTE calls 7Ch or 7Dh.Interrupt handlingNMI Non-maskable interruptThis interrupt is reserved for use by the Z80 operating system and cannot beintercepted by the user.INT Interrupt requestWhen an INT is detected the Z80 operating system indirects through locationFFFEh. All unrecognised interrupts are passed to a user INT routine at FFB0h inthe jump table. The address field at FFB1 h should be changed to point to therequired user INT routine. This routine must preserve all registersdata in the locations &3000 to &7FFF are automatically mapped into either themain memory or the 'shadow' screen memory depending on the current screen mode.The state of the memory map is determined by the ROM select latch at &FE30 andthe memory access latch at &FE34. If these registers have been changed, thenthe memory map may not behave as described above.Page&FCPage &FC is mapped to either the external 1 MHz Bus or the cartridges via thesignal INFC (INternal FC). The cartridges will be accessed when bit IFJ is setin the register at &FE34. This page is intended to be used for memory mappedhardware.Page &FDThis page is also mapped to the external 1 MHz Bus or the cartridges by thesignal INFD. This page will access the cartridges when the IFJ bit of theregister &FE34 is set. The page &FD is intended to be used for accessing theremote memory. Note that location &FCFF is reserved as a paging register toallow up to 64k bytes to be accessed through this page.The Second 32k of RAM.The second 32k of RAM does not occupy one contiguous block of addresses, but isallocated as follows:-&3000-&7FFF shadow screen memory - any part of it not required by the currentscreen mode is available for user programs. Access is gained bymanipulating the memory map latch. However, note that thecommand *MOVE will use this area if one of the non-shadowmodes or a shadow mode occupying less than 20k bytes, isbeing used.&8000-&83FF soft-key expansion buffer - not available for any other purpose.PAGE: 84&8400-&88FF VDU workspace which can only be used for VDU routines thatrequire large amounts of workspace, e.g. flood filling. Care mustbe taken to avoid conflicts between different routines of this sort.Commercial software should avoid using these areas.&8900-&8FFF character definitions.&C000-&DBFF paged ROM workspace. The ROMS use service calls to claimthe area. This is a similar procedure to the one used to claimspace above &E00. Static workspace in this area or above &E00should only be used by filing systems although any ROM mayhave private workspace.&DC00-&DCFF MOS CLI buffer - this area is corrupted by all * commands, andits use for other programs is therefore not recommended.&DD00-&DEFF transient utility workspace and it is available for user written* commands and the *MOVE command.&DF00-&DFFF. MOS workspace only. It may not be used for any otherprograms.VDU Workspace&00D0-&00D9: non-transient VDU variables and should not be used by any otherprogram.&00DA-&00E1 : VDU scratch space and not available for other purposes.&0300-&037F VDU workspace. There are two forms of graphics co-ordinate,internal and external. The external graphics co-ordinate is theone used by the BASIC PLOT command. The internal graphicsco-ordinate is derived from the external by taking into account thegraphics origin and scaling so that it is measured in pixels, bothhorizontally and vertically. Graphics co-ordinates are stored infour bytes, with the low byte of the X co-ordinate first.&8400-&87FF VDU workspace in the shadow RAM used as scratch space forflood filling. If the flood fill is active, one of the values0, 1 ,2,3,4,5,6,7,8,9 or A will appear in the location &8601.Therefore any routines that need to use this space must haveone or more values allocated to them by Acorn Services andTraining Department. If a routine in the set changes any byte inthe VDU workspace, it must leave one of its values in the locationPAGE: 85&8601. If the workspace is assumed to contain any valid data, itmust check that location &8601 contains a suitable value. Iflocation &8601 does not contain a valid value then the routinemust take the appropriate action.VDU workspace allocations&0000-&000F scratch space e.g. flood fill.&001 0-&000F not allocated.&8800-&882F non-transient VDU variables.&8830-&88BF VDU scratch space.&88C0-&88FF reserved for future use by non-transient VDU variables.&8900-&8FFF current character definitions.Earlier BBC Microcomputers and the Acorn Electron&00D0-&00D9 VDU variable and returnusing instructions:El enable interruptsRETI return from maskable interrupt routineZ80 MonitorAfter turning on the Z80 and pressing BREAK the following display appears -Acorn TUBE Z80 64K n.nnAcorn DFSBASIC*where n.nn is the version number of the Z80 ROM. The * prompt indicates thatthe Z80 Monitor is running and at this stage all the standard * commands can beentered i.e. *HELP, *FX4 etc. The Z80 Monitor will also recognise the followingadditional commands which allow memory to be examined, changed and smallmachine code programs to be entered directly and tested.PAGE: 123CPMD GO
S In these commands
refers to a hexadecimal address which can enteredas 1 to 4 digits i.e. 3F can be entered as 3F , 03F or 003F. If more than 4hex digits are entered the most significant digits will be truncated i.e.12345 will be treated as 2345. If no address is specified the most recentlyspecified address will be used instead. For all commands any leading spaces orasterisks and trailing spaces will be ignored.CPM - allows the CP/M system to be loaded without resetting any previouslyentered * commands which would occur if CP/M was loaded using CTRL BREAK.i.e. typing *KEY0 D IRAM *KEY1 STAT * .*AM *KEY2 ERA *CPMwould allow the function keys to be defined before starting up CP/M (These keydefinitions would have been reset if CTRL BREAK had been used to load CP/M).D (Dump) - gives a memory dump with character interpretation between the twospecified addresses. At least one space is expected between the start and endaddresses but no space is necessary before the first address. A dump can beterminated at any time by pressing ESCAPE.GO - causes a jump to the specified addressS (Set) - allows memory to be entered and altered from the specified startaddress.No space is needed between the command and the address. The displayedmemory location can be altered by entering valid hex digits which are shiftedin from the right. The command can be terminated by entering any non hexcharacter.To alter more than one location the U P and DOWN cursor keys can be used toincrement or decrement the memory location.Z80 OSWORD callThe Z80 provides an additional OSWORD call with A = 0FFh, to read or writeblocks of I/O processor memory. On entry HL point to the following controlblock:-PAGE: 124HL + 0 Number of OSWORD parameters sent to I/O processor - 0DhHL + 1 Number of OSWORD parameters read from I/O processor - 01hHL + 2 LSB of I/O processor addressHL + 3 .HL +4 .HL + 5 MSB of I/O processor addressHL + 6 LSB of Z80 processor addressHL+7 .HL+8 .HL+9 MSB of Z80 processor addressHL+A LSB of number of bytes to read/writeHL+B MSB of number of bytes to read/writeHL+C Operation type - 0 to write to I/O processor 1 to read from I/O processorThe first two bytes are used by the Z80 operating system and must not bechanged.If the I/O processor uses sixteen-bit addresses only the first two leastsignificant bytes need to be specified.For example, to read I/O processor screen memory (mode 0) into Z80 memory at08000hLD A,0FFh ;OSWORD call 0FFhLD HL,BLOCK ;Set up HL to point to control blockCALL 0FFF1hBLOCK:DEFB 0Dh DEFB 01h DEFW 03000h ;start of screen memory in I/O processor DEFW 0 ;set high word to zero DEFW 08000h ;start of transfer address in Z80 DEFW 0 DEFW 05000h ;size of screen memory(20K) DEFB 1 ;read operationI/O Processor Memory UsageThe following areas of I/O processor memory are reserved and should not becorrupted by any user programs2500h - 25FFh Reserved for use by Z80 OS2600h - 2FFFh Reserved for use by CP/M0070h -0078h Reserved for use by Z80 OSPAGE: 125Screen ControlThere are three techniques that a CP/M application program can use to controltheBBC Microcomputer's screen :BBC Microcomputer Control CodesTerminal Emulator Control CodesGSX FunctionsBBC Microcomputer Control CodesAll of the functions of thes. These are not transient and should only bealtered in keeping with their function.&00DA-&00DF VDU scratch space - it does not need to be preserved betweenVDU calls, and is not preserved across them.&00E0-&00E1 non-transient VDU variables.&0300-&0327 non-transient VDU variables.&0328-&0349 With the exception of &338, which when in teletext mode is anon-transient variable, this area is a VDU scratch space.&034A-&037F non-transient variables.Extending the MOSThere are occasions when the standard MOS facilities do not meet therequirements of a particular application e.g. when additional hardware has beenincluded in the system. For such situations it is possible to extend or insome cases replace most of the MOS functions with user defined ones. It ispossible to make extensions to both the time-dependent and the time-independentfunctions. It is recommended that users become familiar with thetime-independent functions before changing the time-dependent functions whichare more complex.Time-lndependent FunctionsTime-independent functions may be invoked at any time. The main MOS functionsare entered by calling a subroutine (JSR) at the appropriate entry point. (Forexample, OSWORD is entered at &FFF1 .) The actual entry point for the start ofthe function is stored in a vector table. The routine is accessed by anindirect Jump (JMP) command located at the entry point. In the previousexample of OSWORD,PAGE: 86the vector address is &20C and the MOS code at the OSWORD entry point is JMP(&20C). The vectors are stored as a lookup table in RAM at addresses &200-235.The table is initialised on RESET and by substituting vectors which point touser-supplied code it is possible to change the MOS functions.Vectors in co-processorsMost of the MOS calls are available in the operating system of a co-processor.However, it should be borne in mind that although re-directing a vector in theco-processor will only affect the co-processor, re-directing a vector in thehost will affect both the co-processor and the host. For example, interceptingthe OSWRCH command with WRCHV in the host in order to change all lower casecharacters to upper case will change all the output from the host and theco-processor. However, if the intercept takes place in the co-processor thenonly the output from the current application will be changed, anything fromthe filing systems which operate only in the host will remain unchanged.Vectors In Sideways ROM/RAMExtended vectors may be used to point to sideways memory rather than a locationin non-paged memory. This allows the user to specify the ROM (or RAM) slotnumber as well as the target address. The procedure is shown below.a) Using OSBYTE 168 , read the start of the extended vectorspace ().b) Starting at ( + 3*), place the following data intomemory.().< entry point in ROM (most significant byte)>.< ROM slot number >.c) the relevant vector is then changed to.&FF00 + (-&0200)*3/2The vector's location () is selected from the table shown below. Thenumber (-&0200)/2 is called the vector number.PAGE: 87MOS Function Vector TableFunction Entry Point Vecto